Difference between revisions of "Sega Model 2"

Latest revision as of 08:09, 16 November 2024

Sega Model 2

Manufacturer: Sega Enterprises, Ltd.

Variants: Model 2A-CRX, Model 2B-CRX, Model 2C-CRX

Add-ons: DSB1/DSB2 (Model 2C-CRX)

Release	Date	RRP	Code
JP	1993-08	¥2,200,000^[1]	?
US	1994-03	$15,000^[2]	?
UK	1994-03	£16,000^[1]	?

The Sega Model 2 (モデル2) is an arcade system board originally debuted by Sega in 1993 as a successor to the Sega Model 1 board. It is an extension of the Model 1 hardware, most notably introducing the concept of texture-mapped polygons, allowing for more realistic 3D graphics for its time.

The Model 2 board was an important milestone for the arcade industry, and helped launch several key arcade franchises of the 1990s, including Daytona USA, Virtua Cop, Sega Rally Championship, Dead or Alive, Virtua Striker, Cyber Troopers Virtual-On and The House of the Dead. It was succeeded by the Sega Model 3 in 1996.

Hardware

The Model 2 was designed as the direct successor to the Model 1, and like its predecessor was released as a set of printed circuit boards to arcade operators, or packaged in bespoke cabinets created by Sega. It came into existence when General Electric approached Sega with some real-time texture mapping ASICs, which led to a commercial partnership in August 1992^[3]. The board took about a year to produce^[3].

The most noticeable improvement of the Model 2 over the Model 1 is texture mapping, which enables polygons to be painted with bitmap images, as opposed to the limited monotone flat shading that the previous board supported. The Model 2 also introduced the use of texture filtering and texture anti-aliasing,^[4] as well as trilinear filtering.^[2] It was the most powerful game system in its time, equivalent to the power of a PC graphics card in 1998, five years after the Model 2's release.^[2] It can handle 300,000 polygons per second^[3].

There are in fact four versions of the system: the original Model 2, and the Model 2A-CRX, Model 2B-CRX and Model 2C-CRX variants. The Model 2 and 2A-CRX use a custom DSP with internal code for the geometrizer, while 2B-CRX and 2C-CRX use well documented DSPs and upload the geometrizer code at startup to the DSP.

According to Yu Suzuki, the Sega Model 2B-CRX arcade system board developed for Fighting Vipers "has a slightly faster processing speed" and "a higher response to displaying more polygons".^[5]

Technical specifications

Model 2

Board composition: CPU Board, Video Board, Communication Board, ROM Board, Sound Board, Feedback Driver Board^[6]

Revisions: CPU Board 837-10071 (50 MHz), Video Board 837-10072 (50 MHz), Communication Board 837-10537, ROM Board 834-10798, Sound Board 837-8679 (20 MHz), Drive Board 838-10646^[7]

Main CPU: Intel i960-KB @ 25 MHz^[8]^[9]

Fixed-point arithmetic: 32‑bit RISC instructions @ 25 MIPS^[10]
Floating-point unit: 32/64/80‑bit operations @ 13.6 MFLOPS^[9]
Bus width: 32‑bit

Additional CPU: 2x Zilog Z80 (8/16‑bit instructions @ 1.74 MIPS)

Communication Board: 8 MHz^[7]^[11] (1.16 MIPS)
Feedback Driver: 4 MHz^[6] (0.58 MIPS)

Sound

Sound CPU: Motorola 68000 @ 10 MHz (16/32‑bit instructions @ 1.75 MIPS)
Sound chip: 2x Sega 315‑5560 MultiPCM

PCM channels: 56
PCM sample ROM: Up to 16 MB (8 MB per PCM chip)
PCM quality: 16‑bit depth, 44.1 kHz sampling rate (CD quality)^[12]

Sound timer: Yamaha YM3834 @ 8 MHz (Model 2 only)

Graphics

Graphical specifications of the Sega Model 2:^[13]^[6]^[14]

GPU:

6x Fujitsu TGP MB86234
Sega Video Board 837-10072

GPU Geometry Engine DSP coprocessors: 6x Fujitsu TGP MB86234 @ 16 MHz^[15]^[16]^[7]

Revisions: 315‑5673, 315‑5677, 2x 315‑5678, 2x 315‑5679 (later updated with 2x 315‑5679B in 1994)
Coprocessor abilities: Floating decimal point operation function, axis rotation operation function, 3D matrix operation function, ALU, DMA controllers, T&L (transform, clipping, lighting)^[17]
Instruction set: 32‑bit instructions, 480 MIPS (80 MIPS each)^{[n 1]}
Fixed-point arithmetic: 192 MIPS (32 MIPS each)^{[n 2]}
Floating-point units: 96 MFLOPS (16 MFLOPS each)^{[n 3]}
Bus width: 192‑bit (32‑bit each)
Notes: Located on CPU Board. DSP are modified by Sega with custom microcode for coprocessor and T&L capabilities.^[17]

GPU graphics card: Sega Video Board 837-10072 @ 50 MHz^[7]^[19]

Sega Z-sorting & clipping chipset: 315‑5644 (32 MHz), 315‑5645 (32 MHz), 315‑5712 (40 MHz), 2x 315‑5725 (50 MHz)
Lockheed Martin rasterization & texture mapping processors: 315‑5646 (50 MHz), 315‑5647 (50 MHz)
Sega System 24 tilemap engine: 315‑5292 tilemap generator (32 MHz)^[20]^[21]

Display: Up to 50-inch display^[22]
Display resolution: 496×384 pixels, 24 Hz HSync, progressive scan (non-interlaced), double-buffering^[13]

Overscan resolution: 656×496
Pixel clock rate: 19.523 MHz

Refresh rate: 60 Hz, 57.52416 Hz, 30 Hz^[13]

Frame rate: 60 FPS,^[23] 57.52416 FPS, 30 FPS

Color depth: 65,536 (16bpp), 16,777,216 (24bpp),^[24] 256 (8bpp)
Graphical hardware features: Flat shading, texture mapping, perspective correction, texture filtering, texture anti-aliasing, microtexture, diffuse reflection, specular reflection, specular lighting, alpha blending, transparency, rasterization, mipmapping, LOD,^[13] Z-buffering, point sampling, bilinear filtering, trilinear filtering^[2]

Texture map resolution: Up to 1024×2048 pixels
Microtexture size: Up to 128×128 pixels

Arithmetic: 110 MFLOPS (floating-point), 210 MIPS (fixed-point)^{[n 4]}

Additions: 61 million adds/sec (floating-point), 110 million adds/sec (fixed-point)^{[n 5]}
Multiplications: 61 million multiplies/sec (floating-point), 110 million multiplies/sec (fixed-point)^{[n 6]}
Divisions: 30 million divides/sec^{[n 7]}

Geometry transformations: 6 million vertices/sec,^{[n 8]} 2 million polygons/sec^{[n 9]}

Flat lighting: 1.2 million polygons/sec (floating-point),^{[n 10]} 2 million polygons/sec (fixed-point)^{[n 11]}
Specular lighting: 900,000 polygons/sec^{[n 12]}
Gouraud lighting: 880,000 polygons/sec (floating-point),^{[n 13]} 1.5 million polygons/sec (fixed-point)^{[n 14]}

Rendering fillrate: 110 MPixels/s (16bpp), 230 MPixels/s (8bpp), 260 MPixels/s (4bpp)

Polygons: 100 MPixels/s (16bpp), 200 MPixels/s (8bpp)^{[n 15]}
Tilemaps: 15 MPixels/s (16bpp), 30 MPixels/s (8bpp), 61 MPixels/s (4bpp)^{[n 16]}

Polygon rendering performance: 100 MPixels/s, 900,000 vectors/sec
Texture mapping performance: 100 MTexels/s, lighting

900,000 polygons/sec: Specular, 100-texel polygons
500,000 polygons/sec:^[24] Specular, 200-texel polygons
300,000 polygons/sec: All hardware effects,^[27] trilinear filtering,^[2] specular, 300-texel polygons
300,000 polygons/sec: Gouraud shading (software), 32-texel polygons^{[n 17]}

Hardware support: Motion capture

Memory

Memory: Up to 62 MB (10,881 KB main, 35,460 KB video, 16,960 KB audio, 18 KB other)
System RAM: 9776 KB (9.546875 MB)^[13]

Main RAM: 1152 KB (1.125 MB)
VRAM: 5984 KB (1 MB framebuffer VRAM, 64 KB coprocessor buffer SRAM/SDRAM, 4 MB texture SRAM/SDRAM, 128 KB luma, 32 KB geometry, 576 KB tiles, 64 KB colors)
Audio RAM: 576 KB
Other RAM: 2064 KB (16 KB backup SRAM/NVRAM, 2 MB extra RAM)

Internal processor cache: 36.75 KB

CPU cache: 768 bytes^[8]
TGP internal RAM cache: 36 KB (6 KB per TGP)^[16]

Game ROM: Up to 54.25 MB

Main ROM: 9.5 MB (EPROM, MROM)
Video ROM: 28.75 MB (MROM)
Audio ROM: 16 MB (MROM)

Bandwidth

System RAM bandwidth: 982 MB/s

Main RAM bandwidth: 78.7 MB/s

i960: 66.7 MB/s^[30]
Z80: 12 MB/s^{[n 18]}

VRAM bandwidth: 883.34066 MB/s^[7]^[19]

TGP: 384 MB/s^{[n 19]}
Video Board: 499.34066 MB/s

315‑5292 & 315‑5644: 30.769232 MB/s^{[n 20]}
315‑5645: 28.571428 MB/s^{[n 21]}
315‑5646 & 315‑5647: 400 MB/s^{[n 22]}
315‑5712: 40 MB/s^{[n 23]}

Audio RAM bandwidth: 20 MB/s^{[n 24]}

Internal processor cache bandwidth: 484 MB/s

CPU cache: 100 MB/s^{[n 25]}
TGP internal RAM cache: 384 MB/s^{[n 26]}

Game ROM bandwidth: 933–1000 MB/s^{[n 27]}^[7]^[6]

EPROM: 133–200 MB/s^{[n 28]}
MROM: 800 MB/s^{[n 29]}

Model 2A-CRX

Model 2A-CRX, released in 1994, featured upgraded sound capabilities and increased ROM capacity:

Sound CPU: Motorola 68000 @ 12 MHz (16/32‑bit instructions @ 2.1 MIPS)
Sound chip: Yamaha SCSP

PCM channels: 32
PCM sample ROM: Up to 16 MB
PCM quality: 16‑bit depth, 44.1 kHz sampling rate (CD quality)
SCSP features: 128-step DSP, 32 PCM/FM/MIDI/LFO channels

Memory: Up to 142 MB (35,969 KB main, 90,244 KB video, 16,960 KB audio, 2064 KB other)

System RAM: 9776 KB (9.546875 MB)

Main RAM: 1152 KB (1.125 MB)
VRAM: 5984 KB (5.84375 MB)
Audio RAM: 576 KB
Other RAM: 2064 KB (2.015625 MB)

Internal processor cache: 36.75 KB

CPU cache: 768 bytes
TGP internal RAM cache: 36 KB

Game ROM: Up to 132.25 MB (34 MB main, 82.25 MB video,^[37] 16 MB audio)

Model 2B-CRX

Model 2B-CRX, released in 1995, featured upgraded geometry engine DSP coprocessors and increased VRAM:^[13]

GPU Geometry Engine DSP coprocessors: 2x ADSP-21062 SHARC @ 40 MHz^[38]

Coprocessor abilities: Floating decimal point operation function, axis rotation operation function, 3D matrix operation function, SOC, ALU, T&L
Fixed-point instructions: 32‑bit instructions, 80 MIPS (40 MIPS each)
Floating-point units: 32/40‑bit operations, 240 MFLOPS (120 MFLOPS each), 80 MAC operations/sec (40 MACs/sec each)
Data bus width: 96‑bit (48‑bit each)
DMA controllers: 20 DMA channels (10 channels each), 80 MHz memory access (dual memory access) per SHARC, 480 MB/s transfer rate (240 MB/s each)

Lighting calculations: 240 MFLOPS

Flat lighting: 1.8 million polygons/sec (floating-point)^{[n 30]}
Specular lighting: 1.5 million polygons/sec^{[n 31]}
Gouraud lighting: 1.3 million polygons/sec (floating-point)^{[n 32]}

Rendering fillrate: 130 MPixels/s (16bpp), 270 MPixels/s (8bpp), 300 MPixels/s (4bpp)

Polygons: 120 MPixels/s (16bpp),^{[n 33]} 240 MPixels/s (8bpp)
Tilemaps: 15 MPixels/s (16bpp), 30 MPixels/s (8bpp), 61 MPixels/s (4bpp)

Texture mapping performance: 120 MTexels/s, lighting

900,000 polygons/sec: Specular, 130-texel polygons
600,000 polygons/sec: Specular, 200-texel polygons
300,000 polygons/sec: Gouraud shading (software), 32-texel polygons^{[n 34]}

Memory: Up to 150.21 MB (35.125 MB main, 99,332 KB video, 16,960 KB audio, 18 KB other)

System RAM: 18,388 KB (17.957031 MB)^[6]

Main RAM: 1152 KB (1.125 MB)
VRAM: 14,596 KB (1.5 MB framebuffer VRAM, 8228 KB coprocessor buffer SRAM/SDRAM, 4 MB texture SRAM/SDRAM, 64 KB luma, 32 KB geometry, 576 KB tiles, 64 KB colors)
Audio RAM: 576 KB
Other RAM: 2064 KB (2.015625 MB)

Internal processor cache: 512.75 KB

CPU cache: 768 bytes
DSP internal RAM cache: 512 KB SRAM (256 KB per DSP)^[38]

Game ROM: Up to 132.25 MB (34 MB main, 82.25 MB video, 16 MB audio)

System RAM bandwidth: 1.1 GB/s

Main RAM bandwidth: 112 MB/s
VRAM bandwidth: 979.34066 MB/s

SHARC: 480 MB/s (2x 240 MB/s)^[39]
Video Board: 499.34066 MB/s

Audio RAM bandwidth: 20 MB/s

Model 2C-CRX

Model 2C-CRX, released in 1996, featured an upgraded GPU chipset and optional MPEG sound boards:

GPU geometry coprocessors: 2x Fujitsu TGPx4 MB86235 @ 40 MHz^[13]^[40]

Coprocessor capabilities: Geometry Engine DSP, floating decimal point operation function, axis rotation operation function, 3D matrix operation function, ALU, DMA, T&L
Bus width: 192‑bit (96‑bit each; 64‑bit SDRAM, 32‑bit SRAM)

GPU rendering processors: 2x Fujitsu MB86271 AGP (Advanced Graphics Processor) @ 60 MHz^[41]

Capabilities: Hardware rendering, DMA
Fixed-point arithmetic: 32/64‑bit instructions, 240 MIPS (120 MIPS each)

GPU Z-sorters: 2x Fujitsu MB86272^[41]

Capabilities: Z-sorting, clipping

Graphical hardware features: Gouraud shading, hidden surface, Z-buffering, point sampling, bilinear filtering, trilinear filtering^[42]
Rendering fillrate: 200 MPixels/s (16bpp), 400 MPixels/s (8bpp), 430 MPixels/s (4bpp)

Polygons: 188 MPixels/s (16bpp),^{[n 35]} 376 MPixels/s (8bpp)
Tilemaps: 15 MPixels/s (16bpp), 30 MPixels/s (8bpp), 61 MPixels/s (4bpp)

Texture mapping performance: 188 MTexels/s, lighting, specular,^[13] alpha blending^[40]

900,000 polygons/sec: 150-texel polygons^{[n 36]}
600,000 polygons/sec: Z-sorting,^{[n 37]} 400-texel polygons
520,000 polygons/sec: Gouraud shading,^{[n 38]} 150-texel polygons^{[n 39]}
360,000 polygons/sec: Gouraud shading, Z-sorting,^{[n 40]} 300-texel polygons

Optional MPEG sound board: DSB1

Sound CPU: Zilog Z80 (8/16‑bit instructions)
Sound chip: NEC µD65654GF102

Optional MPEG sound board: DSB2

Sound CPU: Motorola 68000 (16/32‑bit instructions)
Sound chip: NEC µD65654GF102

List of games

Other

Ultimate Domain (unreleased) - Developed by Atlus. Previewed in Mean Machines Sega #51.

History

The Model 2's development was led by famed game designer Yu Suzuki and his team at Sega AM2^[46] as part of a joint project between Sega, Fujitsu and GE Aerospace (acquired by Martin Marietta in 1993, now part of Lockheed Martin). Sega developed the polygon geometry engine in-house^[14], using Fujitsu coprocessors DSP coprocessors that were modified with Sega's custom microcode for hardware T&L capabilities^[17] (it would be years before hardware T&L would appear on consumer home systems). This was then combined with GE Aerospace's expensive texture-mapping technology,^[14] which Suzuki's team condensed into a more affordable chipset.

Suzuki stated that the Model 2's texture mapping chip originated "from military equipment from Lockheed Martin, which was formerly General Electric Aerial & Space's textural mapping technology. It cost $2 million USD to use the chip. It was part of flight-simulation equipment that cost $32 million. I asked how much it would cost to buy just the chip and they came back with $2 million. And I had to take that chip and convert it for video game use, and make the technology available for the consumer at 5,000 yen ($50)" per machine. He said "it was tough but we were able to make it for 5,000 yen. Nobody at Sega believed me when I said I wanted to purchase this technology for our games."^[46] Suzuki stated that, in "the end," it "was a hit and the industry gained mass-produced texture-mapping as a result." For Virtua Fighter 2, he also utilized motion capture technology, introducing it to the game industry.^[47]

There were also issues working on the new CPU,^[46] the Intel i960-KB, which had just released in 1993^[9]. Suzuki stated that when working "on a brand new CPU, the debugger doesn't exist yet. The latest hardware doesn't work because it's full of bugs. And even if a debugger exists, the debugger itself is full of bugs. So, I had to debug the debugger. And of course with new hardware there's no library or system, so I had to create all of that, as well. It was a brutal cycle."^[46]

In a late 1998 interview, Read3D's Jon Lenyo, a former employee of GE Aerospace (later Lockheed Martin), stated that Sega's development for the Model 2 can be traced back as early as November 1990, when he and other GE Aerospace employees visited Sega and demonstrated the trilinear texture filtering and shading capabilities of their technology. As Sega was already working on the Sega Model 1 internally, they eventually incorporated GE Aerospace's technology into the Model 2.^[2]

The arcade board debuted along with Daytona USA, a game which was finished and copyrighted in 1993, and debuted at the Amusement Machine Show 1993^[48].

Despite its high price tag of around $15,000 (equivalent to $25,000 in 2014), the Model 2 platform was very successful. It featured some of the highest grossing arcade games of all time, including Daytona USA, Virtua Fighter 2, Cyber Troopers Virtual-On, The House of the Dead, and Dead or Alive, to name a few. Sega sold over 33,000 units of the Model 2 in its first year,^[49] followed by 65,000 units annually,^[2] and eventually sold over 130,000 units by 1996, amounting to $2 billion revenue from hardware cabinet sales^{[n 41]} (over $3 billion with inflation), making it one of the best-selling arcade systems of all time.

The Model 2 was succeeded in 1996 by the Sega Model 3, which in turn was succeeded by the Sega NAOMI, Sega Hikaru and Sega NAOMI 2.

Production credits

Hiroshi Yagi

Source:

Developer mentions^[52]

Magazine articles

Main article: Sega Model 2/Magazine articles.

Photo gallery

CPU
Video PCB
A typical ROM (Virtua Cop)
Model 2A CPU
Model 2A video PCB
Model 2A ROM (Dead or Alive)
Model 2B CPU/Video PCB
Model 2B filter PCB
Model 2B communications PCB
A Model 2B ROM
Model 2C PCB
Official Sega of Japan photograph of the Model 2B CRX

Notes

↑ [5 instructions per cycle^[18] 5 instructions per cycle^[18]]
↑ MAC (multiply–accumulate) operation (multiply and add) per cycle^[18]
↑ [1 operation per cycle (2 cycles per MAC operation)^[18] 1 operation per cycle (2 cycles per MAC operation)^[18]]
↑ [TGP: 96 MFLOPS, 192 MIPS^[16]
i960: 13.6 MFLOPS, 25 MIPS^[9] TGP: 96 MFLOPS, 192 MIPS^[16]
i960: 13.6 MFLOPS, 25 MIPS^[9]]
↑ [TGP: 48 million adds/sec (floating-point), 96 million adds/sec (fixed-point)^[25]
i960: 13.6 million adds/sec (floating-point), 25 million adds/sec (fixed-point) TGP: 48 million adds/sec (floating-point), 96 million adds/sec (fixed-point)^[25]
i960: 13.6 million adds/sec (floating-point), 25 million adds/sec (fixed-point)]
↑ [TGP: 48 million multiplies/sec (floating-point), 96 million multiplies/sec (fixed-point)^[25]
i960: 13.6 million multiplies/sec (floating-point), 25 million multiplies/sec (fixed-point) TGP: 48 million multiplies/sec (floating-point), 96 million multiplies/sec (fixed-point)^[25]
i960: 13.6 million multiplies/sec (floating-point), 25 million multiplies/sec (fixed-point)]
↑ [Z-sorting & clipping chipset, 32 MHz Z-sorting & clipping chipset, 32 MHz]
↑ [TGP: 5,333,333 vertices/sec, 18 cycles (9 MAC operations) per vertex^[13]
i960: 755,555 vertices/sec, 18 floating-point operations (9 MAC operations) per vertex TGP: 5,333,333 vertices/sec, 18 cycles (9 MAC operations) per vertex^[13]
i960: 755,555 vertices/sec, 18 floating-point operations (9 MAC operations) per vertex]
↑ [3 vertices per triangle polygon 3 vertices per triangle polygon]
↑ [TGP: 1,043,478 polygons/sec, 92 cycles (46 MAC operations) per polygon^[13]
i960: 147,826 polygons/sec, 92 floating-point operations (46 MAC operations) per polygon TGP: 1,043,478 polygons/sec, 92 cycles (46 MAC operations) per polygon^[13]
i960: 147,826 polygons/sec, 92 floating-point operations (46 MAC operations) per polygon]
↑ [46 cycles (46 MAC operations) per polygon^[13] 46 cycles (46 MAC operations) per polygon^[13]]
↑ [102 cycles (51 MAC operations) per polygon^[13] 102 cycles (51 MAC operations) per polygon^[13]]
↑ [TGP: 774,193 polygons/sec, 124 cycles (62 MAC operations) per polygon^[13]^[26]
i960: 109,677 polygons/sec, 124 floating-point operations (62 MAC operations) per polygon TGP: 774,193 polygons/sec, 124 cycles (62 MAC operations) per polygon^[13]^[26]
i960: 109,677 polygons/sec, 124 floating-point operations (62 MAC operations) per polygon]
↑ [62 cycles (62 MAC operations) per polygon^[13]^[26] 62 cycles (62 MAC operations) per polygon^[13]^[26]]
↑ [400 MB/s polygon rendering bandwidth (2x 32‑bit, 50 MHz) 400 MB/s polygon rendering bandwidth (2x 32‑bit, 50 MHz)]
↑ [30.769232 MB/s tilemap generator bandwidth (2x 16‑bit, 7.692308 MHz) 30.769232 MB/s tilemap generator bandwidth (2x 16‑bit, 7.692308 MHz)]
↑ [163 cycles (124 cycles geometry, 39 raster operations) per polygon, 175 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 271 cycles per 32-pixel polygon (3 cycles per pixel) 163 cycles (124 cycles geometry, 39 raster operations) per polygon, 175 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 271 cycles per 32-pixel polygon (3 cycles per pixel)]
↑ [2x 8‑bit, 8/4 MHz 2x 8‑bit, 8/4 MHz]
↑ [6x 32‑bit, 16 MHz^[31] 6x 32‑bit, 16 MHz^[31]]
↑ [2x 16‑bit, 7.692308 MHz^[32] 2x 16‑bit, 7.692308 MHz^[32]]
↑ [16‑bit, 14.285714 MHz^[33] 16‑bit, 14.285714 MHz^[33]]
↑ [2x 32‑bit, 50 MHz 2x 32‑bit, 50 MHz]
↑ [8‑bit, 40 MHz^[34] 8‑bit, 40 MHz^[34]]
↑ [16‑bit, 10 MHz 16‑bit, 10 MHz]
↑ [32‑bit, 25 MHz 32‑bit, 25 MHz]
↑ [6x 32‑bit, 16 MHz 6x 32‑bit, 16 MHz]
↑ [5x 32‑bit 5x 32‑bit]
↑ [32‑bit, 33–50 MHz, 20–30 ns^[35]^[36] 32‑bit, 33–50 MHz, 20–30 ns^[35]^[36]]
↑ [4x 32‑bit, 50 MHz 4x 32‑bit, 50 MHz]
↑ [46 MAC operations per polygon:^[13] 1,739,130 polygons/sec (SHARC), 147,826 polygons/sec (i960) 46 MAC operations per polygon:^[13] 1,739,130 polygons/sec (SHARC), 147,826 polygons/sec (i960)]
↑ [51 MAC operations per polygon^[13] 51 MAC operations per polygon^[13]]
↑ [62 MAC operations per polygon:^[13]^[26] 1,290,322 polygons/sec (SHARC), 109,677 polygons/sec (i960) 62 MAC operations per polygon:^[13]^[26] 1,290,322 polygons/sec (SHARC), 109,677 polygons/sec (i960)]
↑ [2 megapixels per frame 2 megapixels per frame]
↑ [101 cycles (62 cycles geometry, 39 raster operations) per polygon, 113 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 209 cycles per 32-pixel polygon (3 cycles per pixel) 101 cycles (62 cycles geometry, 39 raster operations) per polygon, 113 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 209 cycles per 32-pixel polygon (3 cycles per pixel)]
↑ [94 megapixels/sec per GPU^[43] 94 megapixels/sec per GPU^[43]]
↑ [88 cycles per polygon,^[44] 266 fixed-point instructions per polygon, 450,000 150-pixel polygons/sec per GPU^[45] 88 cycles per polygon,^[44] 266 fixed-point instructions per polygon, 450,000 150-pixel polygons/sec per GPU^[45]]
↑ [272 floating-point operations per polygon 272 floating-point operations per polygon]
↑ [151 cycles per polygon^[44] 151 cycles per polygon^[44]]
↑ [250,000 150-pixel polygons/sec per GPU^[45] 250,000 150-pixel polygons/sec per GPU^[45]]
↑ [438 floating-point operations per polygon 438 floating-point operations per polygon]
↑ [130,000 units^[50] at $15,000 each^[2]^[51] 130,000 units^[50] at $15,000 each^[2]^[51]] (Wayback Machine: 2014-11-04 19:07)

References

↑ ^1.0 ^1.1 Mean Machines Sega, "August 1994" (UK; 1994-06-30), page 93
↑ ^2.0 ^2.1 ^2.2 ^2.3 ^2.4 ^2.5 ^2.6 ^2.7 Second Hand Smoke: One up, two down (October 22, 1999)
↑ ^3.0 ^3.1 ^3.2 Edge, "June 1994" (UK; 1994-04-28), page 49
↑ IGN PRESENTS THE HISTORY OF SEGA (page 8)
↑ File:SSM_UK_02.pdf, page 21
↑ ^6.0 ^6.1 ^6.2 ^6.3 ^6.4 Sega Model 2 (MAME)
↑ ^7.0 ^7.1 ^7.2 ^7.3 ^7.4 ^7.5 Sega PCB
↑ ^8.0 ^8.1 File:I960 datasheet.pdf
↑ ^9.0 ^9.1 ^9.2 ^9.3 File:80960KB datasheet.pdf
↑ File:I960 datasheet.pdf, page 2
↑ http://pdf.datasheetarchive.com/indexerfiles/Scans-068/DSA2IH00225160.pdf
↑ File:ST-077-R2-052594.pdf
↑ ^13.00 ^13.01 ^13.02 ^13.03 ^13.04 ^13.05 ^13.06 ^13.07 ^13.08 ^13.09 ^13.10 ^13.11 ^13.12 ^13.13 ^13.14 ^13.15 ^13.16 Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)
↑ ^14.0 ^14.1 ^14.2 Next Generation, "November 1995" (US; 1995-10-24), page 16
↑ Sega Model 2 ROM Dump
↑ ^16.0 ^16.1 ^16.2 File:MB86232 datasheet.pdf
↑ ^17.0 ^17.1 ^17.2 TGP (MAME)
↑ ^18.0 ^18.1 ^18.2 File:MB86232 datasheet.pdf, page 32
↑ ^19.0 ^19.1 Sega Model 2 Video Board
↑ Sega 16‑Bit Common Hardware, MAME
↑ Sega System 24 Hardware Notes (2013-06-16)
↑ Electronic Gaming Monthly, "June 1994" (US; 1994-xx-xx), page 68
↑ File:VirtuaFighter2 Model2 Flyer.pdf, page 2
↑ ^24.0 ^24.1 Saturn maybe not so stellar (Game Zero Magazine)
↑ ^25.0 ^25.1 File:MB86232 datasheet.pdf, page 33
↑ ^26.0 ^26.1 ^26.2 Design of Digital Systems and Devices (pages 95-97)
↑ File:DaytonaUSA Model2 Flyer.pdf, page 2
↑ ^28.0 ^28.1 Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
↑ ^29.0 ^29.1 File:32XUSHardwareManual.pdf, page 76
↑ File:80960KB datasheet.pdf, page 7
↑ File:TC5588P datasheet.pdf
↑ File:TC518128CPL datasheet.pdf
↑ File:MB84256A datasheet.pdf
↑ http://pdf.datasheetarchive.com/datasheetsmain/Datasheets-39/DSA-764435.pdf
↑ File:AM27C1024 datasheet.pdf
↑ File:MX27C1024 datasheet.pdf
↑ Dynamite Cop (MAME)
↑ ^38.0 ^38.1 File:ADSP-2106 datasheet.pdf
↑ File:ADSP-2106 datasheet.pdf, page 4
↑ ^40.0 ^40.1 File:3DGraphicsProcessorChipSet.pdf
↑ ^41.0 ^41.1 File:3DGraphicsProcessorChipSet.pdf, page 4
↑ File:3D-CG System with Video Texturing.pdf
↑ File:3DGraphicsProcessorChipSet.pdf, page 12
↑ ^44.0 ^44.1 File:3DGraphicsProcessorChipSet.pdf, page 8
↑ ^45.0 ^45.1 File:3DGraphicsProcessorChipSet.pdf, page 11
↑ ^46.0 ^46.1 ^46.2 ^46.3 http://www.1up.com/features/disappearance-suzuki-part-1 (archive.today)
↑ Yu Suzuki recalls using military tech to make Virtua Fighter 2
↑ Electronic Gaming Monthly, "October 1993" (US; 1993-xx-xx), page 222
↑ Press release: 1995-03-20: Lockheed Martin 3D Graphics Accelerator offers real-time PC visual system performance
↑ http://www.real3d.com/sega.html (Wayback Machine: 1997-12-10 08:32)
↑ http://assemblergames.com/forums/showthread.php?47028-Early-concept-of-Daytona-USA-at-Summer-CES-1993-Not-on-Model-2-but-Compu-Scene (Wayback Machine: 2014-11-04 19:07)
↑ https://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)

Sega arcade boards
Originating in arcades
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 VIC Dual G80 Zaxxon VCO Object System 1 LaserDisc Appoooh Hang-On System 2 System 16 OutRun Gigas X Board Y Board System 24 System 18 System 32 Model 1 Model 2 H1 Board Model 3
Console-based hardware
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SG-1000 System E System C Mega-Tech System Mega Play Sega Titan Video NAOMI Hikaru NAOMI 2 Atomiswave System SP Chihiro Triforce
PC-based hardware
05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Lindbergh Europa-R RingEdge RingWide RingEdge 2 Nu Nu 1.1 Nu 2 ALLS

[5_instructions_per_cycle.7F.27.22.60UNIQ--ref-0000003A-QINU.60.22.27.7F-19] [5 instructions per cycle^[18] 5 instructions per cycle^[18]]

[.5B.5Bwikipedia:Multiply.E2.80.93accumulate_operation.7CMAC_.28multiply.E2.80.93accumulate.29_operation.5D.5D_.28multiply_and_add.29_per_cycle.7F.27.22.60UNIQ--ref-0000003E-QINU.60.22.27.7F-20] MAC (multiply–accumulate) operation (multiply and add) per cycle^[18]

[1_operation_per_cycle_.282_cycles_per_MAC_operation.29.7F.27.22.60UNIQ--ref-00000042-QINU.60.22.27.7F-21] [1 operation per cycle (2 cycles per MAC operation)^[18] 1 operation per cycle (2 cycles per MAC operation)^[18]]

[TGP:_96_MFLOPS.2C_192_MIPS.7F.27.22.60UNIQ--ref-00000056-QINU.60.22.27.7F_.3Cbr.3E_i960:_13.6_MFLOPS.2C_25_MIPS.7F.27.22.60UNIQ--ref-00000059-QINU.60.22.27.7F-28] [TGP: 96 MFLOPS, 192 MIPS^[16]
i960: 13.6 MFLOPS, 25 MIPS^[9] TGP: 96 MFLOPS, 192 MIPS^[16]
i960: 13.6 MFLOPS, 25 MIPS^[9]]

[TGP:_48_million_adds.2Fsec_.28floating-point.29.2C_96_million_adds.2Fsec_.28fixed-point.29.7F.27.22.60UNIQ--ref-0000005D-QINU.60.22.27.7F_.3Cbr.3E_i960:_13.6_million_adds.2Fsec_.28floating-point.29.2C_25_million_adds.2Fsec_.28fixed-point.29-30] [TGP: 48 million adds/sec (floating-point), 96 million adds/sec (fixed-point)^[25]
i960: 13.6 million adds/sec (floating-point), 25 million adds/sec (fixed-point) TGP: 48 million adds/sec (floating-point), 96 million adds/sec (fixed-point)^[25]
i960: 13.6 million adds/sec (floating-point), 25 million adds/sec (fixed-point)]

[TGP:_48_million_multiplies.2Fsec_.28floating-point.29.2C_96_million_multiplies.2Fsec_.28fixed-point.29.7F.27.22.60UNIQ--ref-00000061-QINU.60.22.27.7F_.3Cbr.3E_i960:_13.6_million_multiplies.2Fsec_.28floating-point.29.2C_25_million_multiplies.2Fsec_.28fixed-point.29-31] [TGP: 48 million multiplies/sec (floating-point), 96 million multiplies/sec (fixed-point)^[25]
i960: 13.6 million multiplies/sec (floating-point), 25 million multiplies/sec (fixed-point) TGP: 48 million multiplies/sec (floating-point), 96 million multiplies/sec (fixed-point)^[25]
i960: 13.6 million multiplies/sec (floating-point), 25 million multiplies/sec (fixed-point)]

[Z-sorting_.26_clipping_chipset.2C_32_MHz-32] [Z-sorting & clipping chipset, 32 MHz Z-sorting & clipping chipset, 32 MHz]

[TGP:_5.2C333.2C333_vertices.2Fsec.2C_18_cycles_.289_MAC_operations.29_per_vertex.7F.27.22.60UNIQ--ref-00000064-QINU.60.22.27.7F_.3Cbr.3E_i960:_755.2C555_vertices.2Fsec.2C_18_floating-point_operations_.289_MAC_operations.29_per_vertex-33] [TGP: 5,333,333 vertices/sec, 18 cycles (9 MAC operations) per vertex^[13]
i960: 755,555 vertices/sec, 18 floating-point operations (9 MAC operations) per vertex TGP: 5,333,333 vertices/sec, 18 cycles (9 MAC operations) per vertex^[13]
i960: 755,555 vertices/sec, 18 floating-point operations (9 MAC operations) per vertex]

[3_vertices_per_triangle_polygon-34] [3 vertices per triangle polygon 3 vertices per triangle polygon]

[TGP:_1.2C043.2C478_polygons.2Fsec.2C_92_cycles_.2846_MAC_operations.29_per_polygon.7F.27.22.60UNIQ--ref-00000067-QINU.60.22.27.7F_.3Cbr.3E_i960:_147.2C826_polygons.2Fsec.2C_92_floating-point_operations_.2846_MAC_operations.29_per_polygon-35] [TGP: 1,043,478 polygons/sec, 92 cycles (46 MAC operations) per polygon^[13]
i960: 147,826 polygons/sec, 92 floating-point operations (46 MAC operations) per polygon TGP: 1,043,478 polygons/sec, 92 cycles (46 MAC operations) per polygon^[13]
i960: 147,826 polygons/sec, 92 floating-point operations (46 MAC operations) per polygon]

[46_cycles_.2846_MAC_operations.29_per_polygon.7F.27.22.60UNIQ--ref-00000069-QINU.60.22.27.7F-36] [46 cycles (46 MAC operations) per polygon^[13] 46 cycles (46 MAC operations) per polygon^[13]]

[102_cycles_.2851_MAC_operations.29_per_polygon.7F.27.22.60UNIQ--ref-0000006B-QINU.60.22.27.7F-37] [102 cycles (51 MAC operations) per polygon^[13] 102 cycles (51 MAC operations) per polygon^[13]]

[TGP:_774.2C193_polygons.2Fsec.2C_124_cycles_.2862_MAC_operations.29_per_polygon.7F.27.22.60UNIQ--ref-0000006D-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000006E-QINU.60.22.27.7F_.3Cbr.3E_i960:_109.2C677_polygons.2Fsec.2C_124_floating-point_operations_.2862_MAC_operations.29_per_polygon-39] [TGP: 774,193 polygons/sec, 124 cycles (62 MAC operations) per polygon^[13]^[26]
i960: 109,677 polygons/sec, 124 floating-point operations (62 MAC operations) per polygon TGP: 774,193 polygons/sec, 124 cycles (62 MAC operations) per polygon^[13]^[26]
i960: 109,677 polygons/sec, 124 floating-point operations (62 MAC operations) per polygon]

[62_cycles_.2862_MAC_operations.29_per_polygon.7F.27.22.60UNIQ--ref-00000070-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000071-QINU.60.22.27.7F-40] [62 cycles (62 MAC operations) per polygon^[13]^[26] 62 cycles (62 MAC operations) per polygon^[13]^[26]]

[400_MB.2Fs_polygon_rendering_bandwidth_.282x_32.E2.80.91bit.2C_50_MHz.29-41] [400 MB/s polygon rendering bandwidth (2x 32‑bit, 50 MHz) 400 MB/s polygon rendering bandwidth (2x 32‑bit, 50 MHz)]

[30.769232_MB.2Fs_tilemap_generator_bandwidth_.282x_16.E2.80.91bit.2C_7.692308_MHz.29-42] [30.769232 MB/s tilemap generator bandwidth (2x 16‑bit, 7.692308 MHz) 30.769232 MB/s tilemap generator bandwidth (2x 16‑bit, 7.692308 MHz)]

[163_cycles_.28124_cycles_geometry.2C_39_raster_operations.29_per_polygon.2C_175_cycles_per_4-scanline_polygon_.283_operations.2Fscanline_per_polygon.29.2C.7F.27.22.60UNIQ--ref-0000007A-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000007D-QINU.60.22.27.7F_271_cycles_per_32-pixel_polygon_.283_cycles_per_pixel.29-46] [163 cycles (124 cycles geometry, 39 raster operations) per polygon, 175 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 271 cycles per 32-pixel polygon (3 cycles per pixel) 163 cycles (124 cycles geometry, 39 raster operations) per polygon, 175 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 271 cycles per 32-pixel polygon (3 cycles per pixel)]

[2x_8.E2.80.91bit.2C_8.2F4.26nbsp.3BMHz-48] [2x 8‑bit, 8/4 MHz 2x 8‑bit, 8/4 MHz]

[6x_32.E2.80.91bit.2C_16.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-0000008E-QINU.60.22.27.7F-50] [6x 32‑bit, 16 MHz^[31] 6x 32‑bit, 16 MHz^[31]]

[2x_16.E2.80.91bit.2C_7.692308.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-00000092-QINU.60.22.27.7F-52] [2x 16‑bit, 7.692308 MHz^[32] 2x 16‑bit, 7.692308 MHz^[32]]

[16.E2.80.91bit.2C_14.285714.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-00000096-QINU.60.22.27.7F-54] [16‑bit, 14.285714 MHz^[33] 16‑bit, 14.285714 MHz^[33]]

[2x_32.E2.80.91bit.2C_50.26nbsp.3BMHz-55] [2x 32‑bit, 50 MHz 2x 32‑bit, 50 MHz]

[8.E2.80.91bit.2C_40.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-00000099-QINU.60.22.27.7F.5B.5BCategory:External_PDF_reference.5D.5D-57] [8‑bit, 40 MHz^[34] 8‑bit, 40 MHz^[34]]

[16.E2.80.91bit.2C_10.26nbsp.3BMHz-58] [16‑bit, 10 MHz 16‑bit, 10 MHz]

[32.E2.80.91bit.2C_25.26nbsp.3BMHz-59] [32‑bit, 25 MHz 32‑bit, 25 MHz]

[6x_32.E2.80.91bit.2C_16.26nbsp.3BMHz-60] [6x 32‑bit, 16 MHz 6x 32‑bit, 16 MHz]

[5x_32.E2.80.91bit-61] [5x 32‑bit 5x 32‑bit]

[32.E2.80.91bit.2C_33.E2.80.9350_MHz.2C_20.E2.80.9330_.5B.5Bwikipedia:Nanosecond.7Cns.5D.5D.7F.27.22.60UNIQ--ref-000000A3-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000A6-QINU.60.22.27.7F-64] [32‑bit, 33–50 MHz, 20–30 ns^[35]^[36] 32‑bit, 33–50 MHz, 20–30 ns^[35]^[36]]

[4x_32.E2.80.91bit.2C_50_MHz-65] [4x 32‑bit, 50 MHz 4x 32‑bit, 50 MHz]

[46_MAC_operations_per_polygon:.7F.27.22.60UNIQ--ref-000000AE-QINU.60.22.27.7F_1.2C739.2C130_polygons.2Fsec_.28SHARC.29.2C_147.2C826_polygons.2Fsec_.28i960.29-68] [46 MAC operations per polygon:^[13] 1,739,130 polygons/sec (SHARC), 147,826 polygons/sec (i960) 46 MAC operations per polygon:^[13] 1,739,130 polygons/sec (SHARC), 147,826 polygons/sec (i960)]

[51_MAC_operations_per_polygon.7F.27.22.60UNIQ--ref-000000B0-QINU.60.22.27.7F-69] [51 MAC operations per polygon^[13] 51 MAC operations per polygon^[13]]

[62_MAC_operations_per_polygon:.7F.27.22.60UNIQ--ref-000000B2-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000B3-QINU.60.22.27.7F_1.2C290.2C322_polygons.2Fsec_.28SHARC.29.2C_109.2C677_polygons.2Fsec_.28i960.29-70] [62 MAC operations per polygon:^[13]^[26] 1,290,322 polygons/sec (SHARC), 109,677 polygons/sec (i960) 62 MAC operations per polygon:^[13]^[26] 1,290,322 polygons/sec (SHARC), 109,677 polygons/sec (i960)]

[2_megapixels_per_frame-71] [2 megapixels per frame 2 megapixels per frame]

[101_cycles_.2862_cycles_geometry.2C_39_raster_operations.29_per_polygon.2C_113_cycles_per_4-scanline_polygon_.283_operations.2Fscanline_per_polygon.29.2C.7F.27.22.60UNIQ--ref-000000B6-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000B9-QINU.60.22.27.7F_209_cycles_per_32-pixel_polygon_.283_cycles_per_pixel.29-72] [101 cycles (62 cycles geometry, 39 raster operations) per polygon, 113 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 209 cycles per 32-pixel polygon (3 cycles per pixel) 101 cycles (62 cycles geometry, 39 raster operations) per polygon, 113 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[28]^[29] 209 cycles per 32-pixel polygon (3 cycles per pixel)]

[94_megapixels.2Fsec_per_GPU.7F.27.22.60UNIQ--ref-000000D1-QINU.60.22.27.7F-78] [94 megapixels/sec per GPU^[43] 94 megapixels/sec per GPU^[43]]

[88_cycles_per_polygon.2C.7F.27.22.60UNIQ--ref-000000D9-QINU.60.22.27.7F_266_fixed-point_instructions_per_polygon.2C_450.2C000_150-pixel_polygons.2Fsec_per_GPU.7F.27.22.60UNIQ--ref-000000DC-QINU.60.22.27.7F-81] [88 cycles per polygon,^[44] 266 fixed-point instructions per polygon, 450,000 150-pixel polygons/sec per GPU^[45] 88 cycles per polygon,^[44] 266 fixed-point instructions per polygon, 450,000 150-pixel polygons/sec per GPU^[45]]

[272_floating-point_operations_per_polygon-82] [272 floating-point operations per polygon 272 floating-point operations per polygon]

[151_cycles_per_polygon.7F.27.22.60UNIQ--ref-000000E1-QINU.60.22.27.7F-83] [151 cycles per polygon^[44] 151 cycles per polygon^[44]]

[250.2C000_150-pixel_polygons.2Fsec_per_GPU.7F.27.22.60UNIQ--ref-000000E5-QINU.60.22.27.7F-84] [250,000 150-pixel polygons/sec per GPU^[45] 250,000 150-pixel polygons/sec per GPU^[45]]

[438_floating-point_operations_per_polygon-85] [438 floating-point operations per polygon 438 floating-point operations per polygon]

[130.2C000_units.7F.27.22.60UNIQ--ref-000000FD-QINU.60.22.27.7F_at_.2415.2C000_each.7F.27.22.60UNIQ--ref-000000FE-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000FF-QINU.60.22.27.7F-92] [130,000 units^[50] at $15,000 each^[2]^[51] 130,000 units^[50] at $15,000 each^[2]^[51]] (Wayback Machine: 2014-11-04 19:07)

[:File:MeanMachinesSega22UK.pdf_p93-1] 1.0 ^1.1 Mean Machines Sega, "August 1994" (UK; 1994-06-30), page 93

[.5Bhttp:.2F.2Fwww.thg.ru.2Fsmoke.2F19991022.2Fprint.html_Second_Hand_Smoke:_One_up.2C_two_down_.28October_22.2C_1999.29.5D-2] 2.0 ^2.1 ^2.2 ^2.3 ^2.4 ^2.5 ^2.6 ^2.7 Second Hand Smoke: One up, two down (October 22, 1999)

[:File:Edge_UK_009.pdf_p49-3] 3.0 ^3.1 ^3.2 Edge, "June 1994" (UK; 1994-04-28), page 49

[.5Bhttp:.2F.2Fign.com.2Farticles.2F2009.2F04.2F21.2Fign-presents-the-history-of-sega.3Fpage.3D8_IGN_PRESENTS_THE_HISTORY_OF_SEGA_.28page_8.29.5D-4] IGN PRESENTS THE HISTORY OF SEGA (page 8)

[:File:SSM_UK_02.pdf_p21-5] File:SSM_UK_02.pdf, page 21

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fmodel2.cpp_Sega_Model_2_.28MAME.29.5D-6] 6.0 ^6.1 ^6.2 ^6.3 ^6.4 Sega Model 2 (MAME)

[.5Bhttp:.2F.2Fwww.tvspels-nostalgi.com.2Fpcb_sega.htm_Sega_PCB.5D-7] 7.0 ^7.1 ^7.2 ^7.3 ^7.4 ^7.5 Sega PCB

[:File:I960_datasheet.pdf_p-8] 8.0 ^8.1 File:I960 datasheet.pdf

[:File:80960KB_datasheet.pdf_p-9] 9.0 ^9.1 ^9.2 ^9.3 File:80960KB datasheet.pdf

[:File:I960_datasheet.pdf_p2-10] File:I960 datasheet.pdf, page 2

[http:.2F.2Fpdf.datasheetarchive.com.2Findexerfiles.2FScans-068.2FDSA2IH00225160.pdf-11] ttp://pdf.datasheetarchive.com/indexerfiles/Scans-068/DSA2IH00225160.pdf

[:File:ST-077-R2-052594.pdf_p-12] File:ST-077-R2-052594.pdf

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fvideo.2Fmodel2.cpp_Sega_Model_2_Geometry_Engine_and_3D_Rasterizer_.28MAME.29.5D-13] 13.00 ^13.01 ^13.02 ^13.03 ^13.04 ^13.05 ^13.06 ^13.07 ^13.08 ^13.09 ^13.10 ^13.11 ^13.12 ^13.13 ^13.14 ^13.15 ^13.16 Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)

[:File:NextGeneration_US_11.pdf_p16-14] 14.0 ^14.1 ^14.2 Next Generation, "November 1995" (US; 1995-10-24), page 16

[.5Bhttp:.2F.2Fmembers.iinet.net.au.2F.7Elantra9jp1_nbn.2Fgurudumps.2Fm2status.2Findex.html_Sega_Model_2_ROM_Dump.5D-15] Sega Model 2 ROM Dump

[:File:MB86232_datasheet.pdf_p-16] 16.0 ^16.1 ^16.2 File:MB86232 datasheet.pdf

[.5Bhttp:.2F.2Fwiki.mamedev.org.2Findex.php.2FTGP:Index_TGP_.28MAME.29.5D-17] 17.0 ^17.1 ^17.2 TGP (MAME)

[:File:MB86232_datasheet.pdf_p32-18] 18.0 ^18.1 ^18.2 File:MB86232 datasheet.pdf, page 32

[.5Bhttp:.2F.2Fhico-srv004.pixhotel.fr.2Fsites.2Fdefault.2Ffiles.2Fgamoovernet.2F20110520120039-lapin252-IMG-0112.JPG_Sega_Model_2_Video_Board.5D-22] 19.0 ^19.1 Sega Model 2 Video Board

[.5Bhttps:.2F.2Fgithub.com.2Fbji.2Flibmame.2Fblob.2Fmaster.2Fold.2Fsrc.2Fmame.2Fvideo.2Fsegaic16.c_Sega_16.E2.80.91Bit_Common_Hardware.5D.2C_.5B.5BMAME.5D.5D-23] Sega 16‑Bit Common Hardware, MAME

[Sega_System_24_Hardware_Notes_.282013-06-16.29-24] Sega System 24 Hardware Notes (2013-06-16)

[:File:EGM_US_059.pdf_p68-25] Electronic Gaming Monthly, "June 1994" (US; 1994-xx-xx), page 68

[:File:VirtuaFighter2_Model2_Flyer.pdf_p2-26] File:VirtuaFighter2 Model2 Flyer.pdf, page 2

[.5Bhttp:.2F.2Fwww.gamezero.com.2Fteam-0.2Fwhats_new.2Fpast.2Fnews9504.html_Saturn_maybe_not_so_stellar_.28.27.27Game_Zero_Magazine.27.27.29.5D-27] 24.0 ^24.1 Saturn maybe not so stellar (Game Zero Magazine)

[:File:MB86232_datasheet.pdf_p33-29] 25.0 ^25.1 File:MB86232 datasheet.pdf, page 33

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA95_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28pages_95-97.29.5D-38] 26.0 ^26.1 ^26.2 Design of Digital Systems and Devices (pages 95-97)

[:File:DaytonaUSA_Model2_Flyer.pdf_p2-43] File:DaytonaUSA Model2 Flyer.pdf, page 2

[.5Bhttp:.2F.2Fsirkan.iit.bme.hu.2F.7Eszirmay.2Fabbas.pdf.23page.3D53_Transformation_Of_Rendering_Algorithms_For_Hardware_Implementation_.28page_53.29.5D-44] 28.0 ^28.1 Transformation Of Rendering Algorithms For Hardware Implementation (page 53)

[:File:32XUSHardwareManual.pdf_p76-45] 29.0 ^29.1 File:32XUSHardwareManual.pdf, page 76

[:File:80960KB_datasheet.pdf_p7-47] File:80960KB datasheet.pdf, page 7

[:File:TC5588P_datasheet.pdf_p-49] File:TC5588P datasheet.pdf

[:File:TC518128CPL_datasheet.pdf_p-51] File:TC518128CPL datasheet.pdf

[:File:MB84256A_datasheet.pdf_p-53] File:MB84256A datasheet.pdf

[http:.2F.2Fpdf.datasheetarchive.com.2Fdatasheetsmain.2FDatasheets-39.2FDSA-764435.pdf-56] ttp://pdf.datasheetarchive.com/datasheetsmain/Datasheets-39/DSA-764435.pdf

[:File:AM27C1024_datasheet.pdf_p-62] File:AM27C1024 datasheet.pdf

[:File:MX27C1024_datasheet.pdf_p-63] File:MX27C1024 datasheet.pdf

[.5Bhttp:.2F.2Fmamedb.blu-ferret.co.uk.2Fgame.2Fdynamcop_Dynamite_Cop_.28MAME.29.5D-66] Dynamite Cop (MAME)

[:File:ADSP-2106_datasheet.pdf_p-67] 38.0 ^38.1 File:ADSP-2106 datasheet.pdf

[:File:ADSP-2106_datasheet.pdf_p4-73] File:ADSP-2106 datasheet.pdf, page 4

[:File:3DGraphicsProcessorChipSet.pdf_p-74] 40.0 ^40.1 File:3DGraphicsProcessorChipSet.pdf

[:File:3DGraphicsProcessorChipSet.pdf_p4-75] 41.0 ^41.1 File:3DGraphicsProcessorChipSet.pdf, page 4

[:File:3D-CG_System_with_Video_Texturing.pdf_p-76] File:3D-CG System with Video Texturing.pdf

[:File:3DGraphicsProcessorChipSet.pdf_p12-77] File:3DGraphicsProcessorChipSet.pdf, page 12

[:File:3DGraphicsProcessorChipSet.pdf_p8-79] 44.0 ^44.1 File:3DGraphicsProcessorChipSet.pdf, page 8

[:File:3DGraphicsProcessorChipSet.pdf_p11-80] 45.0 ^45.1 File:3DGraphicsProcessorChipSet.pdf, page 11

[http:.2F.2Farchive.is.2F35o4a-86] 46.0 ^46.1 ^46.2 ^46.3 http://www.1up.com/features/disappearance-suzuki-part-1 (archive.today)

[.5Bhttp:.2F.2Fwww.gamasutra.com.2Fview.2Fnews.2F228512.2FYu_Suzuki_recalls_using_military_tech_to_make_Virtua_Fighter_2.php_Yu_Suzuki_recalls_using_military_tech_to_make_Virtua_Fighter_2.5D-87] Yu Suzuki recalls using military tech to make Virtua Fighter 2

[:File:EGM_US_051.pdf_p222-88] Electronic Gaming Monthly, "October 1993" (US; 1993-xx-xx), page 222

[Press_release:_1995-03-20:_Lockheed_Martin_3D_Graphics_Accelerator_offers_real-time_PC_visual_system_performance-89] Press release: 1995-03-20: Lockheed Martin 3D Graphics Accelerator offers real-time PC visual system performance

[http:.2F.2Fweb.archive.org.2Fweb.2F19971210083243.2Fhttp:.2F.2Fwww.real3d.com.2Fsega.html-90] ttp://www.real3d.com/sega.html (Wayback Machine: 1997-12-10 08:32)

[https:.2F.2Fweb.archive.org.2Fweb.2F20141104190719.2Fhttp:.2F.2Fassemblergames.com.2Fforums.2Fshowthread.php.3F47028-Early-concept-of-Daytona-USA-at-Summer-CES-1993-Not-on-Model-2-but-Compu-Scene-91] ttp://assemblergames.com/forums/showthread.php?47028-Early-concept-of-Daytona-USA-at-Summer-CES-1993-Not-on-Model-2-but-Compu-Scene (Wayback Machine: 2014-11-04 19:07)

[https:.2F.2Fweb.archive.org.2Fweb.2F20210205150032.2Fhttps:.2F.2Fwww.4gamer.net.2Fgames.2F999.2FG999905.2F20210126043.2F-93] ttps://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)

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@@ Line 3: / Line 3: @@
 | consoleimage=Model2 cpu.jpg
 | name=
-| maker=[[Sega]]
+| maker=[[Sega Enterprises, Ltd.]]
 | distributor=
 | variants=[[#Model 2A-CRX|Model 2A-CRX]], [[#Model 2B-CRX|Model 2B-CRX]], [[#Model 2C-CRX|Model 2C-CRX]]
@@ Line 18: / Line 18: @@
 }}
 }}
-The '''Sega Model 2''' is an [[arcade]] system board originally debuted by [[Sega]] in 1993 as a successor to the [[Sega Model 1]] board. It is an extension of the Model 1 hardware, most notably introducing the concept of texture-mapped polygons, allowing for more realistic 3D graphics for its time.
+The '''Sega Model 2''' (モデル2) is an [[arcade]] system board originally debuted by [[Sega]] in 1993 as a successor to the [[Sega Model 1]] board. It is an extension of the Model 1 hardware, most notably introducing the concept of texture-mapped polygons, allowing for more realistic 3D graphics for its time.
-The Model 2 board was an important milestone for the arcade industry, and helped launch several key arcade franchises of the 1990s, including ''[[Daytona USA]]'', ''[[Virtua Cop]]'', ''[[Sega Rally Championship]]'', ''[[Dead or Alive]]'', ''[[Virtua Striker]]'', ''[[Cyber Troopers Virtual-On]]'' and ''[[The House of the Dead]]''.
+The Model 2 board was an important milestone for the arcade industry, and helped launch several key arcade franchises of the 1990s, including ''[[Daytona USA]]'', ''[[Virtua Cop]]'', ''[[Sega Rally Championship]]'', ''[[Dead or Alive]]'', ''[[Virtua Striker]]'', ''[[Cyber Troopers Virtual-On]]'' and ''[[The House of the Dead]]''. It was succeeded by the [[Sega Model 3]] in 1996.
 ==Hardware==
@@ Line 48: / Line 48: @@
 {{multicol|
 * Sound CPU: [[Motorola 68000]] @ 10&nbsp;MHz (16/32‑bit instructions @ 1.75&nbsp;MIPS)
-* [[wikipedia:Sound chip|Sound chip]]: 2x [[SegaPCM|Sega 315‑5560 Custom MultiPCM]]
+* [[wikipedia:Sound chip|Sound chip]]: 2x [[Yamaha YMW258-F|Sega 315‑5560 MultiPCM]]
 :* [[Pulse-code modulation|PCM]] channels: 56
 :* PCM sample [[ROM]]: Up to 16&nbsp;[[Byte|MB]] (8&nbsp;MB per PCM chip)
@@ Line 148: / Line 148: @@
 * Sound CPU: Motorola 68000 @ 12&nbsp;MHz (16/32‑bit instructions @ 2.1&nbsp;MIPS)
 * [[wikipedia:Sound chip|Sound chip]]: [[Saturn Custom Sound Processor|Yamaha SCSP]]
-:* PCM channels: 56
+:* PCM channels: 32
 :* PCM sample ROM: Up to 16&nbsp;MB
 :* PCM quality: 16‑bit depth, 44.1&nbsp;kHz sampling rate (CD quality)
@@ Line 247: / Line 247: @@
 *''[[Virtua Cop 2]]'' (1995)
 *''[[Dead or Alive]]'' (1996)
-*''[[Dynamite Baseball]]'' (1996)
 *''[[Dynamite Cop]]'' (1996)
-*''[[Pilot Kids]]'' (1999)
 *''[[Virtua Fighter 2.1]]'' (1996)
 *''[[Motor Raid]]'' (1997)
 *''[[Zero Gunner]]'' (1997)
+*''[[Hanguk Pro Yagu 98]]'' (1998)
+*''[[Pilot Kids]]'' (1999)
 }}
@@ Line 305: / Line 305: @@
 The Model 2 was succeeded in 1996 by the [[Sega Model 3]], which in turn was succeeded by the [[Sega NAOMI]], [[Sega Hikaru]] and [[Sega NAOMI 2]].
+==Production credits==
+{{creditstable|
+*[[Hiroshi Yagi]]
+| source=Developer mentions{{ref|https://web.archive.org/web/20210205150032/https://www.4gamer.net/games/999/G999905/20210126043/}}
+| console=Arcade
+}}
 ==Magazine articles==
@@ Line 322: / Line 329: @@
 Model2b rom.jpg|A Model 2B ROM
 Model2c pcb.jpg|Model 2C PCB
+SegaModel2BCRX.jpg|Official [[Sega of Japan]] photograph of the Model 2B CRX
 </gallery>

Difference between revisions of "Sega Model 2"

From Sega Retro

Latest revision as of 08:09, 16 November 2024

Contents

Hardware

Technical specifications

Model 2

Sound

Graphics

Memory

Bandwidth

Model 2A-CRX

Model 2B-CRX

Model 2C-CRX

List of games

Model 2

Model 2A-CRX

Model 2B-CRX

Model 2C-CRX

Other

History

Production credits

Magazine articles

Photo gallery

Notes

References