Difference between revisions of "Sega NAOMI"

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| arcade_date_jp=[[Amusement Machine Show 1998|1998-09]]
 
| arcade_date_jp=[[Amusement Machine Show 1998|1998-09]]
 
| arcade_date_us=1998
 
| arcade_date_us=1998
| arcade_rrp_us=1,995{{ref|[http://www.segatech.com/arcade/naomi1/index.html NAOMI Technical Overview]}}
+
| arcade_rrp_us=1,995{{ref|[https://web.archive.org/web/20010305074013/segatech.com/arcade/naomi1/index.html NAOMI Technical Overview]}}
 
| arcade_date_world=1998
 
| arcade_date_world=1998
 
}}
 
}}
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==Hardware==
 
==Hardware==
The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same [[Hitachi]] [[SuperH|SH-4]] CPU, [[wikipedia:PowerVR|PowerVR Series 2]] GPU ([http://segatech.com/technical/gpu/index.html PVR2DC]), and [[Yamaha]] [[Yamaha Super Intelligent Sound Processor|AICA]] based sound system. While the CPU of the NAOMI and Dreamcast operate at the same clock speed (clock frequency), the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a higher PowerVR2 clock rate, faster [[VRAM]] bandwidth (125 MHz,{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}{{fileref|HY57V161610D datasheet.pdf}} compared to the Dreamcast's 100 MHz), and FPGA providing additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance or for a multi-monitor setup.
+
The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same [[Hitachi]] [[SuperH|SH-4]] CPU and [[Yamaha]] [[Yamaha Super Intelligent Sound Processor|AICA]] based sound system, along with different revisions of the [[wikipedia:PowerVR|PowerVR Series 2]] GPU architecture. While the CPU of the NAOMI and Dreamcast operate at the same clock frequency, the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a faster PowerVR2 graphics processor, faster [[VRAM]] bandwidth,{{ref|125 MHz,{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}{{fileref|HY57V161610D datasheet.pdf}} compared to the Dreamcast's 100 MHz|group=n}} and [[wikipedia:FPGA|FPGA]] with additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance, or for a multi-monitor setup.
  
 
After ''[[The House of the Dead 2]]'', a newer revision of the PowerVR2 graphics chip was used in subsequent NAOMI systems.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}} According to VideoLogic's president and CEO, Hossein Yassaie, in September 1998: "''With Dreamcast, PowerVR set out to create a new standard in 3D graphics for console gaming; now with Sega’s Naomi, we will deliver unprecedented levels of 3D performance to arcade systems''".{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}}
 
After ''[[The House of the Dead 2]]'', a newer revision of the PowerVR2 graphics chip was used in subsequent NAOMI systems.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}} According to VideoLogic's president and CEO, Hossein Yassaie, in September 1998: "''With Dreamcast, PowerVR set out to create a new standard in 3D graphics for console gaming; now with Sega’s Naomi, we will deliver unprecedented levels of 3D performance to arcade systems''".{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}}
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Along with the standard version, three more variants also exist:
 
Along with the standard version, three more variants also exist:
* First Edition — The initial release of NAOMI hardware was housed in an aluminium shell, similar in design to some versions of the earlier [[Model 2]] and [[Model 3]] system hardware. This version is known to be used in [[House of the Dead 2]] arcade machines, with the game ROM board pre-installed inside the case. It is unknown whether this is a unique hardware variant specifically for House of the Dead 2, or whether it is compatible with later NAOMI releases. This prototype uses an earlier revision of the PowerVR2 graphics chip.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
+
* First Edition — The initial release of NAOMI hardware was housed in an aluminium shell, similar in design to some versions of the earlier [[Model 2]] and [[Model 3]] system hardware. This version is known to be used in [[House of the Dead 2]] arcade machines, with the game ROM board pre-installed inside the case. It is unknown whether this is a unique hardware variant specifically for House of the Dead 2, or whether it is compatible with later NAOMI releases. This prototype uses an earlier revision of the PowerVR2 graphics processor.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
 
* Multiboard — Several NAOMI motherboards joined onto a single board which connects the multiple boards together to created a more powerful parallel processing system.
 
* Multiboard — Several NAOMI motherboards joined onto a single board which connects the multiple boards together to created a more powerful parallel processing system.
* Satellite Terminal — independent NAOMI cabinets connected to a master one
+
* Satellite Terminal — independent NAOMI cabinets connected to a master one, used first by ''[[Derby Owners Club]]''.
  
 
NAOMI boards can be used in special game cabinets (NAOMI Universal Cabinet) where a theoretical maximum of sixteen boards can be used in a parallel processing format.
 
NAOMI boards can be used in special game cabinets (NAOMI Universal Cabinet) where a theoretical maximum of sixteen boards can be used in a parallel processing format.
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==Technical Specifications==
 
==Technical Specifications==
 
===NAOMI Specifications===
 
===NAOMI Specifications===
See ''[[Sega Dreamcast#Technical Specifications|Sega Dreamcast Technical Specifications]]'' for more details on the capabilities of the general Dreamcast/Naomi hardware, though the specifications for the Naomi differ from the Dreamcast in various ways, as listed below.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
+
See ''[[Sega Dreamcast#Technical specifications|Sega Dreamcast technical specifications]]'' for more details on the capabilities of the general Dreamcast/Naomi hardware architecture, though the specifications for the Naomi differ from the Dreamcast in various ways, as listed below.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
  
 
{{multicol|
 
{{multicol|
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** Bus width: 128‑bit internal, 64‑bit external
 
** Bus width: 128‑bit internal, 64‑bit external
 
** Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
 
** Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
** Fixed‑point performance: 360&nbsp;[[wikipedia:Instructions per second|MIPS]] <small>(2 instructions/cycle)</small>
+
** Fixed‑point performance: 360&nbsp;[[wikipedia:Instructions per second|MIPS]]{{ref|2 instructions per cycle|group=n}}
** Floating‑point performance: 1.4&nbsp;[[wikipedia:FLOPS|GFLOPS]] <small>(7 FLOPS/cycle)</small>
+
** Floating‑point performance: 1.4&nbsp;[[wikipedia:FLOPS|GFLOPS]]{{ref|7 floating-point operations per cycle|group=n}}
 
* [[wikipedia:Microcontroller|MCU]]:
 
* [[wikipedia:Microcontroller|MCU]]:
 
** Main MCU: [[Sega]] Custom [[Z80]] @ 21.333&nbsp;MHz (8/16‑bit instructions @ 3.093&nbsp;MIPS){{ref|[http://www.drolez.com/retro/ Obsolete Microprocessors]}}
 
** Main MCU: [[Sega]] Custom [[Z80]] @ 21.333&nbsp;MHz (8/16‑bit instructions @ 3.093&nbsp;MIPS){{ref|[http://www.drolez.com/retro/ Obsolete Microprocessors]}}
** I/O Board MCU: [[Toshiba EMI|Toshiba]] TMP90PH44 @ 14.745&nbsp;MHz (8‑bit instructions @ 3.68625&nbsp;MIPS){{fileref|TMP90PH44 datasheet.pdf}}
+
** I/O Board MCU: [[Toshiba]] TMP90PH44 @ 14.745&nbsp;MHz (8‑bit instructions @ 3.68625&nbsp;MIPS){{fileref|TMP90PH44 datasheet.pdf}}
 
** Optional [[cartridge]] MCU: Microchip PIC12C508A/PIC16C621A @ 4/40&nbsp;MHz (8‑bit [[wikipedia:RISC|RISC]] instructions @ 1/5&nbsp;MIPS){{fileref|PIC12C508A datasheet.pdf}}{{fileref|PIC16C621A datasheet.pdf}}
 
** Optional [[cartridge]] MCU: Microchip PIC12C508A/PIC16C621A @ 4/40&nbsp;MHz (8‑bit [[wikipedia:RISC|RISC]] instructions @ 1/5&nbsp;MIPS){{fileref|PIC12C508A datasheet.pdf}}{{fileref|PIC16C621A datasheet.pdf}}
 
* [[wikipedia:Field-programmable gate array|FPGA]]: 2×&nbsp;FPGA{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
 
* [[wikipedia:Field-programmable gate array|FPGA]]: 2×&nbsp;FPGA{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}
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** Cores: 6 cores (SH‑4&nbsp;SIMD, 5&nbsp;PowerVR2 cores)
 
** Cores: 6 cores (SH‑4&nbsp;SIMD, 5&nbsp;PowerVR2 cores)
 
* GPU geometry processor: Hitachi SH-4 SIMD @ 200&nbsp;MHz
 
* GPU geometry processor: Hitachi SH-4 SIMD @ 200&nbsp;MHz
* GPU rasterizer: [[NEC]]-[[wikipedia:Imagination Technologies|VideoLogic]] [[wikipedia:PowerVR#Series 2|PowerVR 2]]  @ 133.3&nbsp;MHz{{ref|[https://github.com/mamedev/historic-mame/blob/master/src/mame/drivers/naomi.c Sega NAOMI (Historic MAME)]}}
+
* GPU rasterizer: [[NEC]]-[[VideoLogic]] [[PowerVR2]]  @ 100&nbsp;MHz{{ref|[https://github.com/mamedev/historic-mame/blob/master/src/mame/drivers/naomi.c Sega NAOMI (Historic MAME)]}}
** Revision: Newer revision of PowerVR2 used in NAOMI systems (after ''[[The House of the Dead 2]]''), scaled with higher clock rate and more PE elements in ISP core, raised polygon performance{{fileref|PowerVR.pdf|page=3}}
+
** Revision: Newer revision of PowerVR2 used in NAOMI systems (after ''[[The House of the Dead 2]]''),{{ref|[https://github.com/mamedev/historic-mame/blob/master/src/mame/drivers/naomi.c Sega NAOMI (Historic MAME)]}} rendering performance doubled{{ref|Scaled for high-end arcade technology,{{fileref|PowerVR.pdf|page=2}} with parallel ISP cores and increased PE processing elements within processor.{{fileref|PowerVR.pdf|page=3}} NAOMI has average fillrate of 1 gigapixel/sec,{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}} twice that of the Dreamcast's average 500 megapixels/sec fillrate.{{fileref|Edge UK 067.pdf|page=11}}|group=n}}
** Clock generator: CY2308SC-3 (133.3&nbsp;MHz, 4× multiplier with 33.3333&nbsp;MHz oscillator){{fileref|CY2308 datasheet.pdf}}
+
** Cores: TA (Tile Accelerator), 2x ISP (Image Synthesis Processors), TSP (Texture & Shading Processor), Triangle Setup [[wikipedia:Floating-point unit|FPU]], [[wikipedia:RAMDAC|RAMDAC]]
** Cores: Tile Accelerator (TA), Image Synthesis Processor (ISP), Texture & Shading Processor (TSP), Triangle Setup FPU, RAMDAC
+
*** Units: 88 rendering units (74 ISP units, 10 TSP units, 3 FPU units, 1 RAMDAC)
*** Units: 50+ rendering units (37+ ISP units, 10 TSP units, 2 FPU units, 1 RAMDAC)
+
** ISP units: 2x ISP Precalc Units, 2x ISP PE Arrays (64 PE processor elements), 2x Depth Accumulation Buffers, 2x Span RLC, 2x Span Sorters, 2x ISP Parameter Cache
** Triangle Setup FPU: 2 FPU rendering units, 266.6 MFLOPS
+
** TSP units: TSP Precalc, Parameter Cache, Texture Cache, Iterator Array, Pixel Processing Engine, Tile Accumulation Buffer, Secondary Accumulation Buffer, Combine & Bump Map Unit, Fog Unit, Alpha Blending Unit{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=110}}
*** ISP Setup FPU: 133.3 MHz, 133.3 MFLOPS, 14 cycles per polygon, 9,521,428 polygons/sec
+
** Triangle Setup FPU: 3 FPU rendering units, 1 [[wikipedia:GFLOPS|GFLOPS]]
*** TSP Setup FPU: 133.3 MHz, 133.3 MFLOPS
+
*** 2x ISP Setup FPU: 100 MHz, 728 [[wikipedia:MFLOPS|MFLOPS]], surface and [[wikipedia:Hidden surface determination|culling]] processing for polygons, 14,285,714 polygons/sec{{ref|14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=95}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=203}}|group=n}}
 +
*** TSP Setup FPU: 100 MHz, 364 MFLOPS, shading and texture processing{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=95}} for tiles processed by ISP{{fileref|PowerVR.pdf|page=3}}
 
** RAMDAC: 230&nbsp;MHz
 
** RAMDAC: 230&nbsp;MHz
 
** Buses: 2 buses at 125 MHz, 64-bit TA Bus for transferring polygons and textures (1 GB/s), 32-bit PVRIF Bus for register memory (500 MB/s)
 
** Buses: 2 buses at 125 MHz, 64-bit TA Bus for transferring polygons and textures (1 GB/s), 32-bit PVRIF Bus for register memory (500 MB/s)
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** Polygons: Stored in double-buffered display lists,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=102}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=152}} 22 bytes per shaded triangle,{{ref|Flat/Gouraud shading, 43 bytes double-buffered|group=n}} 31 bytes per textured triangle,{{ref|Gouraud shading, 62 bytes double-buffered|group=n}} 36 bytes per bump-mapped triangle,{{ref|Textured, Gouraud shading, bump mapping, 72 bytes double-buffered|group=n}} 38 bytes per volume-modified triangle,{{ref|Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered|group=n}} 96 bytes per [[sprite]]{{ref|Sprite, quad, 192 bytes double-buffered|group=n}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=199}}
 
** Polygons: Stored in double-buffered display lists,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=102}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=152}} 22 bytes per shaded triangle,{{ref|Flat/Gouraud shading, 43 bytes double-buffered|group=n}} 31 bytes per textured triangle,{{ref|Gouraud shading, 62 bytes double-buffered|group=n}} 36 bytes per bump-mapped triangle,{{ref|Textured, Gouraud shading, bump mapping, 72 bytes double-buffered|group=n}} 38 bytes per volume-modified triangle,{{ref|Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered|group=n}} 96 bytes per [[sprite]]{{ref|Sprite, quad, 192 bytes double-buffered|group=n}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=199}}
 
** Textures: 32 KB{{ref|8×8 texture, 16 colors|group=n}} to 16 MB (effectively 42–127 MB with texture compression), average 5–10 MB (effectively 40–60 MB with texture compression), 32 bytes{{ref|8×8×4-bit|group=n}} to 386 KB{{ref|1024×1024×24-bit|group=n}}{{fileref|PowerVR2DCFeaturesUnderWindowsCE.pdf|page=9}} or 1026 KB{{ref|2048×2048×16-bit|group=n}} per texture{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=144}}
 
** Textures: 32 KB{{ref|8×8 texture, 16 colors|group=n}} to 16 MB (effectively 42–127 MB with texture compression), average 5–10 MB (effectively 40–60 MB with texture compression), 32 bytes{{ref|8×8×4-bit|group=n}} to 386 KB{{ref|1024×1024×24-bit|group=n}}{{fileref|PowerVR2DCFeaturesUnderWindowsCE.pdf|page=9}} or 1026 KB{{ref|2048×2048×16-bit|group=n}} per texture{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=144}}
** VRAM bandwidth: 1.2 GB/s (effectively up to 3.2–9.5 GB/s with texture compression)
+
** VRAM bandwidth: 1 GB/s (effectively up to 3–7 GB/s with texture compression)
 
** Note: Main RAM also used to store polygon display lists. Textures transferred directly to VRAM. Textures can be streamed directly from high-speed ROM cartridge.{{ref|[http://farm6.staticflickr.com/5471/12172411045_18bfc5912f_c.jpg Hideki Sato Sega Interview (Edge)]}} Main RAM can also optionally be used to store textures.
 
** Note: Main RAM also used to store polygon display lists. Textures transferred directly to VRAM. Textures can be streamed directly from high-speed ROM cartridge.{{ref|[http://farm6.staticflickr.com/5471/12172411045_18bfc5912f_c.jpg Hideki Sato Sega Interview (Edge)]}} Main RAM can also optionally be used to store textures.
* Geometry pipeline:
+
* Floating-point performance: 2.4 GFLOPS
** Geometry bandwidth: 3.2&nbsp;GB/s <small>(SH‑4&nbsp;SIMD)</small>
 
** Floating‑point performance: 1.4&nbsp;GFLOPS <small>(SH‑4&nbsp;SIMD)</small>
 
* Floating-point performance: 1.6666 GFLOPS
 
 
** SH-4 SIMD: 1.4 GFLOPS geometry
 
** SH-4 SIMD: 1.4 GFLOPS geometry
** PowerVR2: 266.6 MFLOPS rendering
+
** PowerVR2: 1 GFLOPS rendering
 +
* Geometry pipeline: SH‑4 SIMD
 +
** Geometry bandwidth: 3.2&nbsp;GB/s
 +
** Floating‑point performance: 1.4&nbsp;GFLOPS
 
* Rendering [[fillrate]]:
 
* Rendering [[fillrate]]:
** 4&nbsp;[[Pixel|GPixels/s]]: Opaque polygons{{ref|[http://web.archive.org/web/20000823204755/computer.org/micro/articles/dreamcast_2.htm Sega Dreamcast: Implementation (IEEE)]}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf}}
+
** 6 [[Pixel|GPixels/s]]: Maximum fillrate for opaque polygons{{ref|32 pixels/cycle per ISP,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=96}} 1 pixel per PE (processor element),{{fileref|PowerVR.pdf|page=3}}{{fileref|Patent US20030025695.pdf}} 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP{{ref|[http://web.archive.org/web/20000823204755/computer.org/micro/articles/dreamcast_2.htm Sega Dreamcast: Implementation (IEEE)]}}|group=n}}
** Over 1&nbsp;GPixel/s: Translucent and opaque polygons{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}}
+
** 1 [[Pixel|GPixel/s]]: Average fillrate for [[wikipedia:Alpha blending|translucent]] and opaque polygons{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}}{{ref|10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP|group=n}}
* Texture fillrate: Over 1&nbsp;[[Texel|GTexel/s]]
+
** 200 [[Pixel|MPixels/s]]: Minimum fillrate for translucent polygons with hardware sort depth of 60{{ref|60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP|group=n}}
* SH-4 Polygon [[wikipedia:Transform and lighting|T&L]] Geometry: 1.4 GFLOPS{{ref|[http://web.archive.org/web/20000823204755/computer.org/micro/articles/dreamcast_2.htm Sega Dreamcast: Implementation (IEEE)]}}{{fileref|SH-4 Software Manual.pdf|page=151}}
+
* Texture fillrate:{{ref|Same as pixel rendering fillrate|group=n}}
** Geometry transformations: 16.6 million vertices/sec,{{ref|12 cycles per vertex (12 cycles division latency){{fileref|SH-4 Software Manual.pdf|page=211}}
+
** 6 [[Texel|GTexels/s]]: Maximum fillrate for opaque polygons
*4 cycles matrix transformation{{fileref|SH-4 Next-Generation DSP Architecture.pdf|page=12}}
+
** 1 [[Texel|GTexel/s]]: Average fillrate for translucent and opaque polygons
*6.2 cycles perspective division: 2 multiplies, 1 divide, 2 FLDI1{{ref|[http://gamedev.allusion.net/docs/kos-current/matrix_8h.html Dreamcast: Basic matrix operations (KallistiOS)]}} (1.6 MACs per cycle,{{fileref|SH-4 Next-Generation DSP Architecture.pdf|page=12}} 1 divide per cycle,{{fileref|SH-4 Software Manual.pdf|page=211}} 1 cycle per FLDI1){{fileref|SH-4 Software Manual.pdf|page=295}}|group=n}} 16 million polygons/s{{ref|N [[wikipedia:Triangle strip|triangle strips]] per N+2 vertices{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=91}}|group=n}}
+
** 200 [[Texel|MTexels/s]]: Minimum fillrate for translucent polygons with hardware sort depth of 60
** Lighting calculations: 13.1 million vertices/s,{{ref|15.2 cycles per vertex: 4 cycles matrix transformation, 6.2 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA96 ''Design of Digital Systems and Devices'' (page 96)]}}{{fileref|SH-4 Software Manual.pdf|page=151}}|group=n}} 13 million polygons/s{{ref|N triangle strips per N+2 vertices|group=n}}{{ref|[http://web.archive.org/web/20000823204755/computer.org/micro/articles/dreamcast_2.htm Sega Dreamcast: Implementation (IEEE)]}}
+
* SH-4 Polygon [[wikipedia:Transform and lighting|T&L]] Geometry: 1.4 GFLOPS
 +
** Matrix transformations: 50 million vertices/s
 +
** Perspective transformations: 16.6 million vertices/sec, 16 million polygons/s
 +
** 1 light source: 14.2 million vertices/s, 14 million polygons/s
 +
** 4 light sources: 6.89 million vertices/s, 6.8 million polygons/s
 
* CLX2 polygon rendering: Front‑facing polygons drawn on screen, not including overdrawn and back‑facing polygons
 
* CLX2 polygon rendering: Front‑facing polygons drawn on screen, not including overdrawn and back‑facing polygons
** 16.6 million vertices/s{{ref|14 ISP FPU cycles per 3 vertices|group=n}}
+
** 16 million vertices/s{{ref|14 cycles per 3 vertices, per ISP FPU|group=n}}
** 9.5 million polygons/s: Lighting, flat shading{{ref|14 ISP FPU cycles per polygon, 158,000–317,000 polygons per scene, 105–420 pixels per poly|group=n}}
+
** 14 million polygons/s: Lighting, [[wikipedia:Flat shading|flat shading]]{{ref|14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon|group=n}}
** 9.5 million polygons/s: Lighting, texture mapping, shadows, modifier volumes{{ref|Bump mapping, 158,000–219,000 polygons per scene, 105 texels per polygon|group=n}}
+
** 12 million polygons/s: Lighting, texture mapping{{ref|Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon|group=n}}
** 8.3 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping{{ref|138,888 polygons per scene, 60 texels per polygon|group=n}}
+
** 10 million polygons/s: Lighting, texture mapping, shadows, modifier volumes{{ref|Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon|group=n}}
** 8.2 million polygons/s: Lighting, texture mapping, anisotropic filtering{{ref|137,664 polgons per scene,{{ref|[http://dknute.livejournal.com/27148.html Homebrew Test]}} 80 texels per polygon|group=n}}
+
** 8.3 million polygons/s: Lighting, texture mapping, [[wikipedia:Gouraud shading|Gouraud shading]], shadows, modifier volumes, bump mapping{{ref|138,888 polygons per scene, 100–700 texels per polygon|group=n}}
 +
** 8.2 million polygons/s: Lighting, texture mapping, [[wikipedia:Anisotropic filtering|anisotropic filtering]]{{ref|137,664 polygons per scene,{{ref|[http://dknute.livejournal.com/27148.html Homebrew Test]}} 100–700 texels per polygon|group=n}}
 +
** 6.2 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping, anisotropic filtering, translucent polygons{{ref|103,000–137,000 polygons per scene, 32 texels per polygon|group=n}}
 
* 2D [[sprite]] capabilities: Sprites rendered as textured translucent quad polygons
 
* 2D [[sprite]] capabilities: Sprites rendered as textured translucent quad polygons
 
** Colors per sprite: 16 colors (4-bit color) to 16,777,216 colors (24-bit color)
 
** Colors per sprite: 16 colors (4-bit color) to 16,777,216 colors (24-bit color)
 
** Sprite sizes: 8×8 [[texel]]s (224 bytes) to 1024×1024 texels (386.2 KB)
 
** Sprite sizes: 8×8 [[texel]]s (224 bytes) to 1024×1024 texels (386.2 KB)
** Sprite fillrate: 133.3 MTexels/s
+
** Sprite fillrate: 200 MTexels/s
** Maximum sprites per frame: 34,713 sprites (8×8, 60 FPS)
+
** Maximum sprites per frame: 52,083 sprites (8×8, 60 FPS)
** Maximum texels per scanline: 9256 texels (60 FPS)
+
** Maximum texels per scanline: 13,888 texels (60 FPS)
** Maximum sprites per scanline: 1157 sprites (60 FPS)
+
** Maximum sprites per scanline: 1736 sprites (60 FPS)
 
}}
 
}}
  
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{{multicol|
 
{{multicol|
 
* Overall memory: 92–506 [[Byte|MB]]
 
* Overall memory: 92–506 [[Byte|MB]]
* System [[RAM]]: 57,408&nbsp;[[Byte|KB]] (56.0625&nbsp;MB)
+
* Internal processor cache: 120.076 [[Byte|KB]]{{ref|122,958 [[byte]]s|group=n}}{{fileref|DreamcastDevBoxSystemArchitecture.pdf}}
 +
** SH4 [[wikipedia:CPU cache|CPU cache]]: 25.564 KB{{ref|26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers|group=n}}
 +
** PowerVR2 [[wikipedia:GPU cache|GPU cache]]: 46 KB{{ref|47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer|group=n}}
 +
** AICA audio cache: 32.011 KB{{ref|32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer|group=n}}
 +
** I/O Board MCU: 16.5&nbsp;KB{{ref|16,896 bytes: 512&nbsp;bytes RAM, 16&nbsp;KB ROM{{fileref|TMP90PH44 datasheet.pdf}}|group=n}}
 +
* System [[RAM]]: 57,408&nbsp;KB (56.0625&nbsp;MB)
 
** Main RAM: 32&nbsp;MB [[wikipedia:SDRAM|SDRAM]]
 
** Main RAM: 32&nbsp;MB [[wikipedia:SDRAM|SDRAM]]
 
** [[VRAM]]: 16&nbsp;MB SDRAM (unified framebuffer/polygon/texture memory)
 
** [[VRAM]]: 16&nbsp;MB SDRAM (unified framebuffer/polygon/texture memory)
 
** Sound RAM: 8&nbsp;MB SDRAM
 
** Sound RAM: 8&nbsp;MB SDRAM
 
** [[SRAM]]: 64&nbsp;[[Byte|KB]]
 
** [[SRAM]]: 64&nbsp;[[Byte|KB]]
* Internal processor cache: 110,286 [[byte]]s (107.701 KB){{fileref|DreamcastDevBoxSystemArchitecture.pdf}}
 
** SH4: 26,178&nbsp;bytes
 
** PowerVR2: 33.625 KB (34,432 bytes)
 
** AICA: 32,780&nbsp;bytes
 
** I/O Board MCU: 16.5&nbsp;KB (512&nbsp;bytes RAM, 16&nbsp;KB ROM){{fileref|TMP90PH44 datasheet.pdf}}
 
 
* System [[ROM]]: 2048.125&nbsp;KB (2&nbsp;MB [[BIOS]] [[EPROM]], 128&nbsp;bytes [[EPROM|EEPROM]])
 
* System [[ROM]]: 2048.125&nbsp;KB (2&nbsp;MB [[BIOS]] [[EPROM]], 128&nbsp;bytes [[EPROM|EEPROM]])
 
* [[Cartridge]] ROM: 34–448 MB
 
* [[Cartridge]] ROM: 34–448 MB
Line 162: Line 169:
 
====Bandwidth====
 
====Bandwidth====
 
{{multicol|
 
{{multicol|
 +
* Internal processor cache bandwidth:
 +
** SH4: 3.2 GB/s{{ref|128‑bit, 200&nbsp;MHz|group=n}}
 +
** PowerVR2: 28 GB/s{{ref|2304‑bit, 100 MHz: 32-bit TA tile buffer,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=165}} 2x 32-bit ISP registers, 32-bit TSP registers,{{ref|[http://mc.pp.se/dc/pvr.html PowerVR (Dreamcast Hardware)]}} 2x 1024-bit ISP PE Arrays,{{fileref|PowerVR.pdf|page=3}} 64-bit TSP Texture Cache,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=96}} 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer|group=n}}
 +
** AICA: 256 MB/s{{ref|32‑bit, 67&nbsp;MHz|group=n}}
 
* RAM/ROM memory bandwidth: 2.636–3.224 GB/s
 
* RAM/ROM memory bandwidth: 2.636–3.224 GB/s
* System RAM bandwidth: 2&nbsp;GB/s <small>(160‑bit)</small>
+
* System RAM bandwidth: 2&nbsp;GB/s
** Main RAM: 800&nbsp;MB/s <small>(64‑bit, 100&nbsp;MHz, 5264165FTT‑A60)</small>{{fileref|HM5264 datasheet.pdf}}
+
** Main RAM: 800&nbsp;MB/s{{ref|64‑bit, 100&nbsp;MHz, Hitachi HM5264165FTT‑A60{{fileref|HM5264 datasheet.pdf}}|group=n}}
** VRAM: 1&nbsp;GB/s <small>(64‑bit, 125&nbsp;MHz, HY57V161610DTC‑8)</small>{{fileref|HY57V161610D datasheet.pdf}}
+
** VRAM: 1&nbsp;GB/s{{ref|64‑bit, 125&nbsp;MHz, [[wikipedia:SK Hynix|Hynix]] HY57V161610DTC‑8{{fileref|HY57V161610D datasheet.pdf}}|group=n}}
** Sound RAM: 132&nbsp;MB/s <small>(16‑bit, 66&nbsp;MHz,{{fileref|DreamcastDevBoxSystemArchitecture.pdf}} KM416S4030)</small>{{fileref|KM416S4030C datasheet.pdf}}
+
** Sound RAM: 132&nbsp;MB/s{{ref|16‑bit, 66&nbsp;MHz,{{fileref|DreamcastDevBoxSystemArchitecture.pdf}} [[Samsung]] KM416S4030{{fileref|KM416S4030C datasheet.pdf}}|group=n}}
** SRAM: 44&nbsp;MB/s <small>(16‑bit, 22&nbsp;MHz, HM62256)</small>{{fileref|HM62256B datasheet.pdf}}
+
** SRAM: 44&nbsp;MB/s{{ref|16‑bit, 22&nbsp;MHz, Hitachi HM62256{{fileref|HM62256B datasheet.pdf}}|group=n}}
* System ROM bandwidth: 24&nbsp;MB/s <small>(32‑bit)</small>
+
* System ROM bandwidth: 24&nbsp;MB/s
** EPROM: 20&nbsp;MB/s <small>(16‑bit, 10&nbsp;MHz)</small>{{fileref|DreamcastDevBoxSystemArchitecture.pdf}}
+
** EPROM: 20&nbsp;MB/s{{ref|16‑bit, 10&nbsp;MHz{{fileref|DreamcastDevBoxSystemArchitecture.pdf}}|group=n}}
** EEPROM: 4&nbsp;MB/s <small>(16‑bit, 2&nbsp;MHz)</small>{{fileref|AT93C46 datasheet.pdf}}
+
** EEPROM: 4&nbsp;MB/s{{ref|16‑bit, 2&nbsp;MHz{{fileref|AT93C46 datasheet.pdf}}|group=n}}
* Cartridge ROM bandwidth: 612&nbsp;MB/s to 1.2&nbsp;GB/s <small>(2×&nbsp;64‑bit connectors, 1×&nbsp;16‑bit connector)</small>
+
* Cartridge ROM bandwidth: 612&nbsp;MB/s to 1.2&nbsp;GB/s{{ref|2×&nbsp;64‑bit connectors, 1×&nbsp;16‑bit connector|group=n}}
** Sega 1998 format: 612&nbsp;MB/s <small>(34&nbsp;MHz)</small>
+
** Sega 1998 format: 612&nbsp;MB/s{{ref|34&nbsp;MHz|group=n}}
** Sega 1999/2005 format: 900&nbsp;MB/s <small>(50&nbsp;MHz)</small>{{fileref|S29GL-N datasheet.pdf}}
+
** Sega 1999/2005 format: 900&nbsp;MB/s{{ref|50&nbsp;MHz{{fileref|S29GL-N datasheet.pdf}}|group=n}}
** Namco 2000 format: 1.2&nbsp;GB/s <small>(66.666667&nbsp;MHz)</small>{{ref|[http://members.iinet.net.au/~lantra9jp1/gurudumps/naomi/index.html Sega NAOMI (ROM Dumping)]}}{{fileref|DA28F640J5 datasheet.pdf}}
+
** Namco 2000 format: 1.2&nbsp;GB/s{{ref|66.666667&nbsp;MHz{{ref|[http://members.iinet.net.au/~lantra9jp1/gurudumps/naomi/index.html Sega NAOMI (ROM Dumping)]}}{{fileref|DA28F640J5 datasheet.pdf}}|group=n}}
 
** Note: High-speed access allows ROM cartridge to effectively be used as RAM.{{ref|[http://farm6.staticflickr.com/5471/12172411045_18bfc5912f_c.jpg Hideki Sato Sega Interview (Edge)]}}
 
** Note: High-speed access allows ROM cartridge to effectively be used as RAM.{{ref|[http://farm6.staticflickr.com/5471/12172411045_18bfc5912f_c.jpg Hideki Sato Sega Interview (Edge)]}}
* Cartridge RAM bandwidth: 28–100 MB/s <small>(8/16‑bit, 28–50 MHz)</small>
+
* Cartridge RAM bandwidth: 28–100 MB/s{{ref|8/16‑bit, 28–50 MHz|group=n}}
* Internal processor cache bandwidth: 7.1884&nbsp;GB/s <small>(384‑bit)</small>
 
** SH4: 3.2 GB/s <small>(128‑bit, 200&nbsp;MHz)</small>
 
** PowerVR2: 3.7324 GB/s <small>(224‑bit, 133.3&nbsp;MHz)</small>
 
** AICA: 256 MB/s <small>(32‑bit, 67&nbsp;MHz)</small>
 
 
}}
 
}}
  
Line 206: Line 213:
 
** Sound RAM: 132&nbsp;MB/s
 
** Sound RAM: 132&nbsp;MB/s
 
** SRAM: 44&nbsp;MB/s
 
** SRAM: 44&nbsp;MB/s
** DIMM RAM: 1.064–2.128 GB/s (1/2×&nbsp;64‑bit, 133&nbsp;MHz){{ref|[http://wiki.arcadeotaku.com/w/Sega_Naomi_DIMM_board_and_GD-ROM Sega NAOMI DIMM board and GD-ROM]}}{{fileref|M366S3323CT0 datasheet.pdf}}
+
** DIMM RAM: 1.064–2.128 GB/s{{ref|1/2×&nbsp;64‑bit, 133&nbsp;MHz{{ref|[http://wiki.arcadeotaku.com/w/Sega_Naomi_DIMM_board_and_GD-ROM Sega NAOMI DIMM board and GD-ROM]}}{{fileref|M366S3323CT0 datasheet.pdf}}|group=n}}
 
}}
 
}}
  
Line 227: Line 234:
 
{{multicol|
 
{{multicol|
 
* GPU: 4–8 core processors (2–4 SH‑4&nbsp;SIMD, 2–4 PowerVR2)
 
* GPU: 4–8 core processors (2–4 SH‑4&nbsp;SIMD, 2–4 PowerVR2)
** Core units: 12–24 units (2–4 SH‑4&nbsp;SIMD, 10–20 PowerVR2 cores)
+
** Cores: 12–24 cores (2–4 SH‑4&nbsp;SIMD, 10–20 PowerVR2 cores)
 
* Display resolution: 2–3 monitors, 640×240 to 2400×608, progressive scan, widescreen JAMMA/[[Dreamcast VGA Adapter|VGA]]
 
* Display resolution: 2–3 monitors, 640×240 to 2400×608, progressive scan, widescreen JAMMA/[[Dreamcast VGA Adapter|VGA]]
 
** Internal resolution: 640×240 to 1600×1200 pixels per board
 
** Internal resolution: 640×240 to 1600×1200 pixels per board
* Geometry pipeline:
+
* Floating-point performance: 4–9 GFLOPS
** Geometry bandwidth: 6–12 GB/s <small>(2–4 SH‑4&nbsp;SIMD)</small>
+
** SH-4 SIMD: 2.8–5.6 GFLOPS geometry
** Floating‑point performance: 2.8–5.6 GFLOPS <small>(2–4 SH‑4&nbsp;SIMD)</small>
+
** PowerVR2: 2–4 GFLOPS rendering
 +
* Geometry pipeline: 2–4 SH‑4 SIMD
 +
** Geometry bandwidth: 6–12 GB/s
 +
** Floating‑point performance: 2.8–5.6 GFLOPS
 
* Rendering fillrate:
 
* Rendering fillrate:
** 8–16 GPixels/s: Opaque polygons
+
** 12–24 GPixels/s: Maximum fillrate for opaque polygons
** 2–4 GPixels/s: Translucent and opaque polygons
+
** 2–4 GPixels/s: Average fillrate for translucent and opaque polygons
* Texture fillrate: 2–4 GTexels/s
+
** 400–800 MPixels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
* Floating-point performance: 3.0666–6.1332 GFLOPS
+
* Texture fillrate:
** SH-4 SIMD: 2.8–5.6 GFLOPS geometry
+
** 12–24 GTexels/s: Maximum fillrate for opaque polygons
** PowerVR2: 266.6–533.2 MFLOPS rendering
+
** 2–4 GTexels/s: Average fillrate for translucent and opaque polygons
 +
** 400–800 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
 
* SH-4 polygon T&L geometry:
 
* SH-4 polygon T&L geometry:
** Geometry transformations: 32–64 million polygons/s
+
** Matrix transformations: 100–200 million vertices/s
** Lighting calculations: 26–52 million polygons/s
+
** Perspective transformations: 32–64 million polygons/s
 +
** Lighting calculations: 28–56 million polygons/s
 
* CLX2 polygon rendering:
 
* CLX2 polygon rendering:
 
** 32–64 million vertices/sec
 
** 32–64 million vertices/sec
** 19–38 million polygons/s: Lighting, flat shading
+
** 28–56 million polygons/s: Lighting, flat shading
** 19–38 million polygons/s: Lighting, texture mapping, shadows, modifier volumes
+
** 24–48 million polygons/s: Lighting, texture mapping
 +
** 20–40 million polygons/s: Lighting, texture mapping, shadows, modifier volumes
 
** 16–32 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping
 
** 16–32 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping
 
** 16–32 million polygons/s: Lighting, texture mapping, anisotropic filtering
 
** 16–32 million polygons/s: Lighting, texture mapping, anisotropic filtering
Line 270: Line 283:
 
====Bandwidth====
 
====Bandwidth====
 
{{multicol|
 
{{multicol|
* System RAM bandwidth: 4–8 GB/s <small>(320/640‑bit)</small>
+
* System RAM bandwidth: 4–8 GB/s
** Main RAM: 1.6–3.2 GB/s <small>(128/256‑bit)</small>
+
** Main RAM: 1.6–3.2 GB/s{{ref|128/256‑bit|group=n}}
** VRAM: 2–4 GB/s <small>(128/256‑bit)</small>
+
** VRAM: 2–4 GB/s{{ref|128/256‑bit|group=n}}
** Sound RAM: 264–528 MB/s <small>(32/64‑bit)</small>
+
** Sound RAM: 264–528 MB/s{{ref|32/64‑bit|group=n}}
** SRAM: 88–176 MB/s <small>(32/64‑bit)</small>
+
** SRAM: 88–176 MB/s{{ref|32/64‑bit|group=n}}
* Internal processor cache bandwidth: 11.1768–22.3536 GB/s <small>(640/1280‑bit)</small>
+
* Internal processor cache bandwidth:
** SH4: 3.2–6.4 GB/s <small>(128/256‑bit)</small>
+
** SH4: 3.2–6.4 GB/s{{ref|128/256‑bit|group=n}}
** PowerVR2: 7.4648–14.9296 GB/s <small>(448/896‑bit)</small>
+
** PowerVR2: 41–83 GB/s
** AICA: 512–1024 MB/s <small>(64/128‑bit)</small>
+
** AICA: 512–1024 MB/s{{ref|64/128‑bit|group=n}}
* System ROM bandwidth: 48–96 MB/s <small>(64/128‑bit)</small>
+
* System ROM bandwidth: 48–96 MB/s
** EPROM: 40–80 MB/s <small>(32/64‑bit)</small>
+
** EPROM: 40–80 MB/s{{ref|32/64‑bit|group=n}}
** EEPROM: 8–16 MB/s <small>(32/64‑bit)</small>
+
** EEPROM: 8–16 MB/s{{ref|32/64‑bit|group=n}}
 
}}
 
}}
  
Line 318: Line 331:
 
**''[[The Typing of the Dead]]'' (1999)
 
**''[[The Typing of the Dead]]'' (1999)
 
*''[[Zombie Revenge]]'' (1998)
 
*''[[Zombie Revenge]]'' (1998)
*''[[Sky Champ]]'' (199?)
 
 
*''[[18 Wheeler: American Pro Trucker]]'' (1999)
 
*''[[18 Wheeler: American Pro Trucker]]'' (1999)
 
*''[[Charge'N'Blast]]'' (1999)
 
*''[[Charge'N'Blast]]'' (1999)
Line 358: Line 370:
 
**''[[StarHorse 2001‏‎]]'' (2001)
 
**''[[StarHorse 2001‏‎]]'' (2001)
 
**''[[StarHorse 2002‏‎]]'' (2002)
 
**''[[StarHorse 2002‏‎]]'' (2002)
*''[[Tokyo Bus Tour]]'' (2000)
+
*''[[Tokyo Bus Guide]]'' (2000)
 
*''[[Virtua NBA]]'' (2000)
 
*''[[Virtua NBA]]'' (2000)
 
*''[[Virtua Striker 2 Ver.2000]]'' (2000)
 
*''[[Virtua Striker 2 Ver.2000]]'' (2000)
Line 367: Line 379:
 
*''[[Inu no Osanpo]]'' (2001)
 
*''[[Inu no Osanpo]]'' (2001)
 
*''[[Zero Gunner 2]]'' (2001)
 
*''[[Zero Gunner 2]]'' (2001)
*''[[Kouchuu Ouja Mushiking: The Battle of the Beetles]]'' (2003)
+
*''[[Mushiking: The King of Beetles]]'' (2003)
**''[[Kouchuu Ouja Mushiking: The King Of Beetle 2K3 2nd]]'' (2003)
 
**''[[Kouchuu Ouja Mushiking II]]'' (2004)
 
**''[[Kouchuu Ouja Mushiking III]]'' (2005)
 
**''[[Kouchuu Ouja Mushiking IV]]'' (2006)
 
**''[[Kouchuu Ouja Mushiking V]]'' (2007)
 
*''[[Oshare Majo Love and Berry: / Fashionable Witch Love and Berry]]'' (2005)
 
*''[[Dynamite Deka EX]]'' (2006)
 
 
*''[[Rhythm Tengoku]]'' (2007)
 
*''[[Rhythm Tengoku]]'' (2007)
 
*''[[Shooting Love 2007]]'' (2007)
 
*''[[Shooting Love 2007]]'' (2007)
 +
* ''[[Manic Panic Ghosts]]'' (2007)
 
*''[[Akatsuki Denkou Senki]]'' (2008)
 
*''[[Akatsuki Denkou Senki]]'' (2008)
*''[[Disney Magical Dance]]'' (2008)
 
 
*''[[Illmatic Envelope]]'' (2008)
 
*''[[Illmatic Envelope]]'' (2008)
 
*''[[Mamoru-kun wa Norowarete Shimatta!]]'' (2008)
 
*''[[Mamoru-kun wa Norowarete Shimatta!]]'' (2008)
Line 460: Line 465:
 
*''[[Kuru Kuru Chameleon]]'' (2006)
 
*''[[Kuru Kuru Chameleon]]'' (2006)
 
*''[[Noukone Puzzle Takoron]]'' (2006)
 
*''[[Noukone Puzzle Takoron]]'' (2006)
*''[[Touch De Zunou]]'' (2006)
 
 
*''[[Trigger Heart Exelica]]'' (2006)
 
*''[[Trigger Heart Exelica]]'' (2006)
 
*''[[Project Cerberus]]'' (moved to PlayStation Portable during development; last seen on NAOMI in 2009)
 
*''[[Project Cerberus]]'' (moved to PlayStation Portable during development; last seen on NAOMI in 2009)
Line 519: Line 523:
 
{{multicol|
 
{{multicol|
 
<references />
 
<references />
}}
+
|cols=3}}
  
 
{{Sega Arcade Boards}}
 
{{Sega Arcade Boards}}
 
{{Dreamcast}}
 
{{Dreamcast}}
 
[[Category:Sega NAOMI]]
 
[[Category:Sega NAOMI]]

Revision as of 18:49, 8 June 2018

Naomi case.jpg
Sega NAOMI
Manufacturer: Sega
Variants: Sega NAOMI GD-ROM, Sega NAOMI Multiboard, Sega Dreamcast, Atomiswave, Sega Aurora
Add-ons: GD-ROM
Release Date RRP Code

The NAOMI (New Arcade Operation Machine Idea) is an arcade system released by Sega in 1998. It was designed as a successor to Sega Model 3 hardware, using a similar architecture to the Sega Dreamcast.

The NAOMI was succeeded by the Sega Hikaru and Sega NAOMI 2 boards, though having out-lasted the NAOMI 2, Hikaru and Sega Aurora. The Sega Chihiro, or possibly even the Sega Lindbergh, could also be seen as successors.

History

The NAOMI debuted at a time when traditional arcades were on a decline, and so was engineered to be a mass-produced, cost-effective machine reliant on large game ROM cartridges which could be interchanged by the arcade operator. This is contrary to systems such as the Model 3, in which each board, despite sharing largely the same specifications, would be bespoke, with the built-in ROMs being flashed with games during the manufacturing process. This is not the first time such an idea was utilised by Sega, but never before had technology been used for a cutting-edge Sega arcade specification.

Unlike most hardware platforms in the arcade industry, NAOMI was widely licensed for use by other manufacturers, many of which were former rivals to Sega, such as Taito, Capcom and Namco. It is also one of the longest-serving arcade boards, being supported from 1998 to 2009. It is a platform where many top-rated Sega franchises were born, including Virtua Tennis, Samba de Amigo, Crazy Taxi and Monkey Ball.

Hardware

The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same Hitachi SH-4 CPU and Yamaha AICA based sound system, along with different revisions of the PowerVR Series 2 GPU architecture. While the CPU of the NAOMI and Dreamcast operate at the same clock frequency, the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a faster PowerVR2 graphics processor, faster VRAM bandwidth,[n 1] and FPGA with additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance, or for a multi-monitor setup.

After The House of the Dead 2, a newer revision of the PowerVR2 graphics chip was used in subsequent NAOMI systems.[1] According to VideoLogic's president and CEO, Hossein Yassaie, in September 1998: "With Dreamcast, PowerVR set out to create a new standard in 3D graphics for console gaming; now with Sega’s Naomi, we will deliver unprecedented levels of 3D performance to arcade systems".[3]

Another key difference between NAOMI and Dreamcast lies in the game-media - the NAOMI primarily uses ROM PC (printed circuit) boards (i.e. large game cartridges) with up to 168 MB of usable data (more expensive but with faster loading), while the Dreamcast uses GD-ROM optical-storage with up to 1GB of storage (at the expense of load times). The NAOMI was extended in 1999 so that it could interface with GD-ROM-based arcade games. This system uses standard PC SDR-DIMM modules which are battery backed-up for storing game data. The game data is read from the GD-ROM at bootup, stored onto the SDR RAM to which the NAOMI reads from during game. This leaves less wear on the GD-ROM drive as it's only used when the memory is empty or corrupted, else it will use the SDR RAM for boot-up every subsequent power on after checking the data integrity. If the battery fails, the system is left turned off for several days or the game GD-ROM is changed, the game will be reloaded from the GD-ROM drive.

Along with the standard version, three more variants also exist:

  • First Edition — The initial release of NAOMI hardware was housed in an aluminium shell, similar in design to some versions of the earlier Model 2 and Model 3 system hardware. This version is known to be used in House of the Dead 2 arcade machines, with the game ROM board pre-installed inside the case. It is unknown whether this is a unique hardware variant specifically for House of the Dead 2, or whether it is compatible with later NAOMI releases. This prototype uses an earlier revision of the PowerVR2 graphics processor.[1]
  • Multiboard — Several NAOMI motherboards joined onto a single board which connects the multiple boards together to created a more powerful parallel processing system.
  • Satellite Terminal — independent NAOMI cabinets connected to a master one, used first by Derby Owners Club.

NAOMI boards can be used in special game cabinets (NAOMI Universal Cabinet) where a theoretical maximum of sixteen boards can be used in a parallel processing format.

The NAOMI multiboard setup uses a different BIOS chip than a regular NAOMI to handle all the boards but the whole system only uses one copy of the game cartridge, of which only four games were released.

Technical Specifications

NAOMI Specifications

See Sega Dreamcast technical specifications for more details on the capabilities of the general Dreamcast/Naomi hardware architecture, though the specifications for the Naomi differ from the Dreamcast in various ways, as listed below.[1]

Main

  • Main CPU: Hitachi SH-4 @ 200 MHz[4][5]
    • Units: 128‑bit SIMD vector unit with graphic functions, 64‑bit floating‑point unit, 32‑bit fixed‑point unit
    • Bus width: 128‑bit internal, 64‑bit external
    • Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
    • Fixed‑point performance: 360 MIPS[n 2]
    • Floating‑point performance: 1.4 GFLOPS[n 3]
  • MCU:
    • Main MCU: Sega Custom Z80 @ 21.333 MHz (8/16‑bit instructions @ 3.093 MIPS)[6]
    • I/O Board MCU: Toshiba TMP90PH44 @ 14.745 MHz (8‑bit instructions @ 3.68625 MIPS)[7]
    • Optional cartridge MCU: Microchip PIC12C508A/PIC16C621A @ 4/40 MHz (8‑bit RISC instructions @ 1/5 MIPS)[8][9]
  • FPGA: 2× FPGA[1]
    • Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz[10]
    • Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6&nbsp[11]

Graphics

  • GPU: 2 core processors (SH‑4 SIMD, PowerVR2)
    • Cores: 6 cores (SH‑4 SIMD, 5 PowerVR2 cores)
  • GPU geometry processor: Hitachi SH-4 SIMD @ 200 MHz
  • GPU rasterizer: NEC-VideoLogic PowerVR2 @ 100 MHz[12]
    • Revision: Newer revision of PowerVR2 used in NAOMI systems (after The House of the Dead 2),[12] rendering performance doubled[n 4]
    • Cores: TA (Tile Accelerator), 2x ISP (Image Synthesis Processors), TSP (Texture & Shading Processor), Triangle Setup FPU, RAMDAC
      • Units: 88 rendering units (74 ISP units, 10 TSP units, 3 FPU units, 1 RAMDAC)
    • ISP units: 2x ISP Precalc Units, 2x ISP PE Arrays (64 PE processor elements), 2x Depth Accumulation Buffers, 2x Span RLC, 2x Span Sorters, 2x ISP Parameter Cache
    • TSP units: TSP Precalc, Parameter Cache, Texture Cache, Iterator Array, Pixel Processing Engine, Tile Accumulation Buffer, Secondary Accumulation Buffer, Combine & Bump Map Unit, Fog Unit, Alpha Blending Unit[16]
    • Triangle Setup FPU: 3 FPU rendering units, 1 GFLOPS
      • 2x ISP Setup FPU: 100 MHz, 728 MFLOPS, surface and culling processing for polygons, 14,285,714 polygons/sec[n 5]
      • TSP Setup FPU: 100 MHz, 364 MFLOPS, shading and texture processing[17] for tiles processed by ISP[14]
    • RAMDAC: 230 MHz
    • Buses: 2 buses at 125 MHz, 64-bit TA Bus for transferring polygons and textures (1 GB/s), 32-bit PVRIF Bus for register memory (500 MB/s)
    • Features: Bump mapping, fog, alpha blending, mipmapping, anti-aliasing, environment mapping, specular effects,[4] normal mapping, tiled rendering, deferred rendering, back‑face culling, hidden surface removal. See Sega Dreamcast Technical Specifications for more details on PowerVR2 graphics system.
  • DAC: Sega 315‑6145 (Rohm BU1426KS) @ 35.4695 MHz[19]
    • Bus width: 24‑bit
  • Display resolution: 320×240 to 800×608 pixels, progressive scan, JAMMA/VGA
    • Internal resolution: 320×240 to 1600×1200 pixels
  • Color depth: 16-bit RGB to 32‑bit ARGB, 65,536 to 16,777,216 colors (24‑bit color) with 8‑bit (256 levels) alpha blending, YUV and RGB color space, color key overlay
  • Framebuffer:
    • Full framebuffer: 320×240×16‑bit (150 KB) to 1600×1200×24‑bit (5625 KB)
    • Strip/Tile buffer: 32×32×16‑bit (4 KB) to 32×32×24‑bit (8 KB)[20]
  • VRAM: 16 MB (effectively up to 42–127 MB with texture compression)
    • Framebuffer: 300–5625 KB (optional), average 1200–1800 KB (640×480, 16/24-bit color, double-buffered)
    • Polygons: Stored in double-buffered display lists,[21][22] 22 bytes per shaded triangle,[n 6] 31 bytes per textured triangle,[n 7] 36 bytes per bump-mapped triangle,[n 8] 38 bytes per volume-modified triangle,[n 9] 96 bytes per sprite[n 10][23]
    • Textures: 32 KB[n 11] to 16 MB (effectively 42–127 MB with texture compression), average 5–10 MB (effectively 40–60 MB with texture compression), 32 bytes[n 12] to 386 KB[n 13][24] or 1026 KB[n 14] per texture[25]
    • VRAM bandwidth: 1 GB/s (effectively up to 3–7 GB/s with texture compression)
    • Note: Main RAM also used to store polygon display lists. Textures transferred directly to VRAM. Textures can be streamed directly from high-speed ROM cartridge.[26] Main RAM can also optionally be used to store textures.
  • Floating-point performance: 2.4 GFLOPS
    • SH-4 SIMD: 1.4 GFLOPS geometry
    • PowerVR2: 1 GFLOPS rendering
  • Geometry pipeline: SH‑4 SIMD
    • Geometry bandwidth: 3.2 GB/s
    • Floating‑point performance: 1.4 GFLOPS
  • Rendering fillrate:
  • Texture fillrate:[n 18]
    • 6 GTexels/s: Maximum fillrate for opaque polygons
    • 1 GTexel/s: Average fillrate for translucent and opaque polygons
    • 200 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
  • SH-4 Polygon T&L Geometry: 1.4 GFLOPS
    • Matrix transformations: 50 million vertices/s
    • Perspective transformations: 16.6 million vertices/sec, 16 million polygons/s
    • 1 light source: 14.2 million vertices/s, 14 million polygons/s
    • 4 light sources: 6.89 million vertices/s, 6.8 million polygons/s
  • CLX2 polygon rendering: Front‑facing polygons drawn on screen, not including overdrawn and back‑facing polygons
    • 16 million vertices/s[n 19]
    • 14 million polygons/s: Lighting, flat shading[n 20]
    • 12 million polygons/s: Lighting, texture mapping[n 21]
    • 10 million polygons/s: Lighting, texture mapping, shadows, modifier volumes[n 22]
    • 8.3 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping[n 23]
    • 8.2 million polygons/s: Lighting, texture mapping, anisotropic filtering[n 24]
    • 6.2 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping, anisotropic filtering, translucent polygons[n 25]
  • 2D sprite capabilities: Sprites rendered as textured translucent quad polygons
    • Colors per sprite: 16 colors (4-bit color) to 16,777,216 colors (24-bit color)
    • Sprite sizes: 8×8 texels (224 bytes) to 1024×1024 texels (386.2 KB)
    • Sprite fillrate: 200 MTexels/s
    • Maximum sprites per frame: 52,083 sprites (8×8, 60 FPS)
    • Maximum texels per scanline: 13,888 texels (60 FPS)
    • Maximum sprites per scanline: 1736 sprites (60 FPS)

Sound

Memory

  • Overall memory: 92–506 MB
  • Internal processor cache: 120.076 KB[n 26][20]
  • System RAM: 57,408 KB (56.0625 MB)
    • Main RAM: 32 MB SDRAM
    • VRAM: 16 MB SDRAM (unified framebuffer/polygon/texture memory)
    • Sound RAM: 8 MB SDRAM
    • SRAM: 64 KB
  • System ROM: 2048.125 KB (2 MB BIOS EPROM, 128 bytes EEPROM)
  • Cartridge ROM: 34–448 MB
    • Sega 1998/1999 format: 34–184 MB (32–176 MB FlashROM/MROM, 0–4 MB EPROM)
    • Namco 2000 format: 136–400 MB (136–256 MB FlashROM, 0–144 MB MROM)
    • Sega 2005 format: 128–448 MB (128–448 MB FlashROM, 0–40 MB EPROM,[31] 128 KB Flash PROM)[32]
  • Cartridge RAM: 32–64 KB SRAM
  • Optional cartridge MCU memory: 793/1888 bytes (25/96 bytes SRAM, 768/1792 bytes EPROM)[8][9]

Bandwidth

  • Internal processor cache bandwidth:
  • RAM/ROM memory bandwidth: 2.636–3.224 GB/s
  • System RAM bandwidth: 2 GB/s
  • System ROM bandwidth: 24 MB/s
  • Cartridge ROM bandwidth: 612 MB/s to 1.2 GB/s[n 40]
    • Sega 1998 format: 612 MB/s[n 41]
    • Sega 1999/2005 format: 900 MB/s[n 42]
    • Namco 2000 format: 1.2 GB/s[n 43]
    • Note: High-speed access allows ROM cartridge to effectively be used as RAM.[26]
  • Cartridge RAM bandwidth: 28–100 MB/s[n 44]

NAOMI GD-ROM Specifications

The NAOMI GD-ROM, released in 1999, is identical to the standard NAOMI, but uses GD-ROM discs for storage instead of ROM cartridges. It comes with a DIMM Board, which is very similar to a ROM cartridge, but with RAM instead of ROM. When a game is installed, the GD ROM content is loaded onto the DIMM Board RAM, so that the game data runs from the DIMM Board rather than the GD-ROM disc.

  • Board composition: Motherboard, Internal ROM Board, Filter Board, I/O Board, DIMM Board
  • Storage: GD-ROM disc drive @ 12× speed, 1 GB per GD-ROM disc
    • GD-ROM transfer rate: 1800 KB/s

Memory

  • Overall memory: 66–570 MB
  • System RAM: 57,408 KB (56.0625 MB)
  • Internal processor cache: 110,286 bytes (107.701 KB)
  • System ROM: 2048.125 KB (2.0001 MB)
  • DIMM Board RAM: 8–512 MB DIMM SDRAM[42]

Bandwidth

  • RAM bandwidth: 3 GB/s
    • Main RAM: 800 MB/s
    • VRAM: 1 GB/s
    • Sound RAM: 132 MB/s
    • SRAM: 44 MB/s
    • DIMM RAM: 1.064–2.128 GB/s[n 45]

NAOMI Multiboard Specifications

The NAOMI Multiboard, released in 1999, stacks together multiple NAOMI system boards for parallel processing in a single arcade system, ranging from 2 to 16 system boards. Since the 16‑board variant is not known to have been used by any games, the following specifications are for the 2‑board and 4‑board variants:

  • Board composition: 2–4 NAOMI system boards

Main

  • CPU: 2–4× Hitachi SH-4 @ 200 MHz
    • Performance: 720–1440 MIPS, 2.8–5.6 GFLOPS
  • MCU: 2–4× Sega Custom Z80 @ 21.333 MHz (8‑bit & 16‑bit instructions @ 6–12 MIPS)
  • FPGA: 4–8× FPGA
    • 2–4× Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz
    • 2–4× Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6 MHz

Graphics

  • GPU: 4–8 core processors (2–4 SH‑4 SIMD, 2–4 PowerVR2)
    • Cores: 12–24 cores (2–4 SH‑4 SIMD, 10–20 PowerVR2 cores)
  • Display resolution: 2–3 monitors, 640×240 to 2400×608, progressive scan, widescreen JAMMA/VGA
    • Internal resolution: 640×240 to 1600×1200 pixels per board
  • Floating-point performance: 4–9 GFLOPS
    • SH-4 SIMD: 2.8–5.6 GFLOPS geometry
    • PowerVR2: 2–4 GFLOPS rendering
  • Geometry pipeline: 2–4 SH‑4 SIMD
    • Geometry bandwidth: 6–12 GB/s
    • Floating‑point performance: 2.8–5.6 GFLOPS
  • Rendering fillrate:
    • 12–24 GPixels/s: Maximum fillrate for opaque polygons
    • 2–4 GPixels/s: Average fillrate for translucent and opaque polygons
    • 400–800 MPixels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
  • Texture fillrate:
    • 12–24 GTexels/s: Maximum fillrate for opaque polygons
    • 2–4 GTexels/s: Average fillrate for translucent and opaque polygons
    • 400–800 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
  • SH-4 polygon T&L geometry:
    • Matrix transformations: 100–200 million vertices/s
    • Perspective transformations: 32–64 million polygons/s
    • Lighting calculations: 28–56 million polygons/s
  • CLX2 polygon rendering:
    • 32–64 million vertices/sec
    • 28–56 million polygons/s: Lighting, flat shading
    • 24–48 million polygons/s: Lighting, texture mapping
    • 20–40 million polygons/s: Lighting, texture mapping, shadows, modifier volumes
    • 16–32 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping
    • 16–32 million polygons/s: Lighting, texture mapping, anisotropic filtering

Sound

Memory

  • System RAM: 112–224 MB
    • Main RAM: 64–128 MB
    • VRAM: 32–64 MB
    • Sound RAM: 16–32 MB
    • SRAM: 64–128 KB
  • Internal processor cache: 220,572–441,144 bytes (215.402–430.804 KB)
  • System ROM: 4096.25–8192.5 KB (4–8 MB BIOS EPROM, 256–512 bytes EEPROM)

Bandwidth

  • System RAM bandwidth: 4–8 GB/s
  • Internal processor cache bandwidth:
    • SH4: 3.2–6.4 GB/s[n 46]
    • PowerVR2: 41–83 GB/s
    • AICA: 512–1024 MB/s[n 48]
  • System ROM bandwidth: 48–96 MB/s

Gallery

First Edition

Main version

List of Games

NAOMI

Distributed by Capcom

Distributed by Namco

NAOMI GD-ROM

Distributed by Capcom

Distributed by Taito

NAOMI Multiboard

NAOMI Satellite Terminal

Promotional material

Notes

  1. [125 MHz,[1][2] compared to the Dreamcast's 100 MHz 125 MHz,[1][2] compared to the Dreamcast's 100 MHz]
  2. [2 instructions per cycle 2 instructions per cycle]
  3. [7 floating-point operations per cycle 7 floating-point operations per cycle]
  4. [Scaled for high-end arcade technology,[13] with parallel ISP cores and increased PE processing elements within processor.[14] NAOMI has average fillrate of 1 gigapixel/sec,[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.[15] Scaled for high-end arcade technology,[13] with parallel ISP cores and increased PE processing elements within processor.[14] NAOMI has average fillrate of 1 gigapixel/sec,[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.[15]]
  5. [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles[17][18] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles[17][18]]
  6. [Flat/Gouraud shading, 43 bytes double-buffered Flat/Gouraud shading, 43 bytes double-buffered]
  7. [Gouraud shading, 62 bytes double-buffered Gouraud shading, 62 bytes double-buffered]
  8. [Textured, Gouraud shading, bump mapping, 72 bytes double-buffered Textured, Gouraud shading, bump mapping, 72 bytes double-buffered]
  9. [Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered]
  10. [Sprite, quad, 192 bytes double-buffered Sprite, quad, 192 bytes double-buffered]
  11. [8×8 texture, 16 colors 8×8 texture, 16 colors]
  12. [8×8×4-bit 8×8×4-bit]
  13. [1024×1024×24-bit 1024×1024×24-bit]
  14. [2048×2048×16-bit 2048×2048×16-bit]
  15. [32 pixels/cycle per ISP,[27] 1 pixel per PE (processor element),[14][28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP[29] 32 pixels/cycle per ISP,[27] 1 pixel per PE (processor element),[14][28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP[29]] (Wayback Machine: 2000-08-23 20:47)
  16. [10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP 10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP]
  17. [60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP 60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP]
  18. [Same as pixel rendering fillrate Same as pixel rendering fillrate]
  19. [14 cycles per 3 vertices, per ISP FPU 14 cycles per 3 vertices, per ISP FPU]
  20. [14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon 14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon]
  21. [Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon]
  22. [Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon]
  23. [138,888 polygons per scene, 100–700 texels per polygon 138,888 polygons per scene, 100–700 texels per polygon]
  24. [137,664 polygons per scene,[30] 100–700 texels per polygon 137,664 polygons per scene,[30] 100–700 texels per polygon]
  25. [103,000–137,000 polygons per scene, 32 texels per polygon 103,000–137,000 polygons per scene, 32 texels per polygon]
  26. [122,958 bytes 122,958 bytes]
  27. [26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers 26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers]
  28. [47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer 47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer]
  29. [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]
  30. [16,896 bytes: 512 bytes RAM, 16 KB ROM[7] 16,896 bytes: 512 bytes RAM, 16 KB ROM[7]]
  31. [128‑bit, 200 MHz 128‑bit, 200 MHz]
  32. [2304‑bit, 100 MHz: 32-bit TA tile buffer,[33] 2x 32-bit ISP registers, 32-bit TSP registers,[34] 2x 1024-bit ISP PE Arrays,[14] 64-bit TSP Texture Cache,[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer 2304‑bit, 100 MHz: 32-bit TA tile buffer,[33] 2x 32-bit ISP registers, 32-bit TSP registers,[34] 2x 1024-bit ISP PE Arrays,[14] 64-bit TSP Texture Cache,[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer]
  33. [32‑bit, 67 MHz 32‑bit, 67 MHz]
  34. [64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60[35] 64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60[35]]
  35. [64‑bit, 125 MHz, Hynix HY57V161610DTC‑8[2] 64‑bit, 125 MHz, Hynix HY57V161610DTC‑8[2]]
  36. [16‑bit, 66 MHz,[20] Samsung KM416S4030[36] 16‑bit, 66 MHz,[20] Samsung KM416S4030[36]]
  37. [16‑bit, 22 MHz, Hitachi HM62256[37] 16‑bit, 22 MHz, Hitachi HM62256[37]]
  38. [16‑bit, 10 MHz[20] 16‑bit, 10 MHz[20]]
  39. [16‑bit, 2 MHz[38] 16‑bit, 2 MHz[38]]
  40. [2× 64‑bit connectors, 1× 16‑bit connector 2× 64‑bit connectors, 1× 16‑bit connector]
  41. [34 MHz 34 MHz]
  42. [50 MHz[39] 50 MHz[39]]
  43. [66.666667 MHz[40][41] 66.666667 MHz[40][41]]
  44. [8/16‑bit, 28–50 MHz 8/16‑bit, 28–50 MHz]
  45. [1/2× 64‑bit, 133 MHz[42][43] 1/2× 64‑bit, 133 MHz[42][43]]
  46. 46.0 46.1 46.2 [128/256‑bit 128/256‑bit]
  47. 47.0 47.1 47.2 47.3 [32/64‑bit 32/64‑bit]
  48. [64/128‑bit 64/128‑bit]

References

  1. 1.0 1.1 1.2 1.3 1.4 Sega NAOMI (MAME)
  2. 2.0 2.1 File:HY57V161610D datasheet.pdf
  3. 3.0 3.1 3.2 Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM
  4. 4.0 4.1 File:NAOMI 1998 Press Release JP.pdf
  5. File:SH-4 Software Manual.pdf
  6. Obsolete Microprocessors
  7. 7.0 7.1 File:TMP90PH44 datasheet.pdf
  8. 8.0 8.1 File:PIC12C508A datasheet.pdf
  9. 9.0 9.1 File:PIC16C621A datasheet.pdf
  10. File:EPF8452A datasheet.pdf
  11. File:EPC1064 datasheet.pdf
  12. 12.0 12.1 Sega NAOMI (Historic MAME)
  13. File:PowerVR.pdf, page 2
  14. 14.0 14.1 14.2 14.3 File:PowerVR.pdf, page 3
  15. File:Edge UK 067.pdf, page 11
  16. File:DreamcastDevBoxSystemArchitecture.pdf, page 110
  17. 17.0 17.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 95
  18. File:DreamcastDevBoxSystemArchitecture.pdf, page 203
  19. File:BU142 datasheet.pdf
  20. 20.0 20.1 20.2 20.3 File:DreamcastDevBoxSystemArchitecture.pdf
  21. File:DreamcastDevBoxSystemArchitecture.pdf, page 102
  22. File:DreamcastDevBoxSystemArchitecture.pdf, page 152
  23. File:DreamcastDevBoxSystemArchitecture.pdf, page 199
  24. File:PowerVR2DCFeaturesUnderWindowsCE.pdf, page 9
  25. File:DreamcastDevBoxSystemArchitecture.pdf, page 144
  26. 26.0 26.1 Hideki Sato Sega Interview (Edge)
  27. 27.0 27.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 96
  28. File:Patent US20030025695.pdf
  29. Sega Dreamcast: Implementation (IEEE) (Wayback Machine: 2000-08-23 20:47)
  30. Homebrew Test
  31. Asian Dynamite (MAME)
  32. File:XCF01S datasheet.pdf
  33. File:DreamcastDevBoxSystemArchitecture.pdf, page 165
  34. PowerVR (Dreamcast Hardware)
  35. File:HM5264 datasheet.pdf
  36. File:KM416S4030C datasheet.pdf
  37. File:HM62256B datasheet.pdf
  38. File:AT93C46 datasheet.pdf
  39. File:S29GL-N datasheet.pdf
  40. Sega NAOMI (ROM Dumping)
  41. File:DA28F640J5 datasheet.pdf
  42. 42.0 42.1 Sega NAOMI DIMM board and GD-ROM
  43. File:M366S3323CT0 datasheet.pdf


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Sega Dreamcast
Topics Technical specifications (Hardware comparison) | History (Development | Release | Decline and legacy | Internet) | List of games | Magazine articles | Promotional material | Merchandise
Hardware Japan (Special) | Western Europe | Eastern Europe | North America | Asia | South America | Australasia | Africa
Add-ons Dreamcast Karaoke | Dreameye
Controllers Controller | Arcade Stick | Fishing Controller | Gun (Dream Blaster) | Race Controller | Maracas Controller (Third-party) | Twin Stick | Keyboard | Mouse | Third-party
Controller Add-ons Jump Pack (Third-party) | Microphone | VMU (4x Memory Card | Third-party)
Development Hardware Dev.Box | Controller Box | Controller Function Checker | Sound Box | GD-Writer | C1/C2 Checker | Dev.Cas | GD-ROM Duplicator
Online Services/Add-ons Dreamarena | SegaNet | WebTV for Dreamcast | Modem | Modular Cable | Modular Extension Cable | Broadband Adapter | Dreamphone
Connector Cables Onsei Setsuzoku Cable | RF Adapter | Scart Cable | S Tanshi Cable | Stereo AV Cable | VGA Box

Dreamcast MIDI Interface Cable | Neo Geo Pocket/Dreamcast Setsuzoku Cable | Taisen Cable

Misc. Hardware Action Replay CDX | Code Breaker | Kiosk | MP3 DC | MP3 DC Audio Player | Official Case | Treamcast
Third-party accessories Controllers | Controller converters | Miscellaneous
Unreleased Accessories DVD Player | Zip Drive | Swatch Access for Dreamcast | VMU MP3 Player
Arcade Variants NAOMI | Atomiswave | Sega Aurora