Difference between revisions of "SH-2"

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SH-2

Designer: Hitachi

The SH-2 is a 32-bit RISC processor developed by Hitachi (and currently produced by Renesas) as part of the SuperH family. It is used by the Sega 32X and the Sega Saturn.

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The Sega Saturn is powered by two SH-2 processors running in a Master/Slave configuration. These particular SH-2 chips run at 28.6364 MHz (versions were developed which ran as high as 40 MHz), and are capable of processing up to 37.227268 MIPS each (1.3 MIPS per MHz),^[1]^[2] for a combined rating of 74.45464 MIPS (MIPS however, is not a true indication of processor performance in many cases). Each SH-2 comes with an internal 4 KB RAM cache in order to speed up processing tasks.

“	The SH-2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles.	„
— Next Generation ^[3]

Technical specifications

Clock rate: 28.63636 MHz^[4]^[5]^[6]
CPU core: 32‑bit RISC instructions/registers, 37.227268 MIPS (1.3 MIPS per MHz),^[1]^[2] up to 2 instructions per cycle^[7]
DMA unit: DMAC (Direct Memory Access Controller),^[8] parallel processing^[9]
2 internal fixed‑point math processors:^[10] MULT multiplier DSP,^[8]^[11]^[12] DIVU division unit,^[8]^[11] parallel processing^[13]

2x MULT multiplier DSP: 57.27272 MOPS^{[fn 1]} fixed-point math (28.63636 MOPS per SH-2)^{[fn 2]}
2x DIVU division units: 16/32/64-bit division,^[13] 1,468,531 divides/sec^{[fn 3]}

Bus width: 64‑bit (2× 32‑bit) internal, 32‑bit external^[16]
Word length: 32-bit
Supports Master/Slave configuration with dual SH-2

Documentation

Hardware manual
Programming manual
Programming manual

Footnotes

↑ [MOPS (million operations per second) MOPS (million operations per second)]
↑ [1 operation per cycle^[14] 1 operation per cycle^[14]]
↑ [39 cycles per divide^[15] 39 cycles per divide^[15]]

References

[MOPS_.28million_operations_per_second.29-14] [MOPS (million operations per second) MOPS (million operations per second)]

[1_operation_per_cycle.7F.27.22.60UNIQ--ref-00000033-QINU.60.22.27.7F-16] [1 operation per cycle^[14] 1 operation per cycle^[14]]

[39_cycles_per_divide.7F.27.22.60UNIQ--ref-0000003A-QINU.60.22.27.7F-18] [39 cycles per divide^[15] 39 cycles per divide^[15]]

[:File:SH-2A.pdf_p2-1] 1.0 ^1.1 File:SH-2A.pdf, page 2

[.5Bhttps:.2F.2Fwww.renesas.com.2Fen-eu.2Fproducts.2Fmicrocontrollers-microprocessors.2Fsuperh.2Fsh7040.2Fsh7040.html_SH7040.2C_SH7041.2C_SH7042.2C_SH7043.2C_SH7044.2C_SH7045.5D.2C_Renesas-2] 2.0 ^2.1 SH7040, SH7041, SH7042, SH7043, SH7044, SH7045, Renesas

[:File:NextGeneration_US_02.pdf_p42-3] Next Generation, "February 1995" (US; 1995-01-24), page 42

[Sega_Saturn_hardware_notes_.282004-04-27.29-4] Sega Saturn hardware notes (2004-04-27)

[:File:Hitachi_SuperH_Programming_Manual.pdf_p-5] File:Hitachi SuperH Programming Manual.pdf

[:File:SH7604_Hardware_Manual.pdf_p-6] File:SH7604 Hardware Manual.pdf

[:File:Hitachi_SuperH_Programming_Manual.pdf_p390-7] File:Hitachi SuperH Programming Manual.pdf, page 390

[:File:SH7604_Hardware_Manual.pdf_p3-8] 8.0 ^8.1 ^8.2 File:SH7604 Hardware Manual.pdf, page 3

[:File:SH7604_Hardware_Manual.pdf_p219-9] File:SH7604 Hardware Manual.pdf, page 219

[:File:Sega_Service_Manual_-_Sega_Saturn_.28PAL.29_-_013-1_-_June_1995.pdf_p-10] File:Sega Service Manual - Sega Saturn (PAL) - 013-1 - June 1995.pdf

[:File:SH7604_Hardware_Manual.pdf_p22-11] 11.0 ^11.1 File:SH7604 Hardware Manual.pdf, page 22

[:File:ST-103-R1-040194.pdf_p23-12] File:ST-103-R1-040194.pdf, page 23

[:File:SH7604_Hardware_Manual.pdf_p303-13] 13.0 ^13.1 File:SH7604 Hardware Manual.pdf, page 303

[:File:Hitachi_SuperH_Programming_Manual.pdf_p31-15] File:Hitachi SuperH Programming Manual.pdf, page 31

[:File:Hitachi_SuperH_Programming_Manual.pdf_p155-17] File:Hitachi SuperH Programming Manual.pdf, page 155

[:File:ST-103-R1-040194.pdf_p-19] File:ST-103-R1-040194.pdf

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[fn 1]

[fn 2]

[fn 3]

[16]

[14]

[15]

@@ Line 6: / Line 6: @@
 | date=
 }}
-The '''SH-2''' is a 32-bit RISC processor developed by [[Hitachi]] (and currently produced by Renesas) as part of the [[SuperH]] family.
+The '''SH-2''' is a 32-bit RISC processor developed by [[Hitachi]] (and currently produced by Renesas) as part of the [[SuperH]] family. It is used by the [[Sega 32X]] and the [[Sega Saturn]].
 {{rewrite}}
-The [[Sega Saturn]] is powered by two [[Hitachi]] SH2, 32-bit RISC processors. These particular [[SuperH|SH-2]] chips run at 28.6364 MHz (versions were developed which ran as high as 40 MHz), and are capable of processing up to 37.22732 million instructions per second (MIPS) each (1.3 MIPS per MHz),{{fileref|SH-2A.pdf|page=2}}{{ref|[https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/superh/sh7040/sh7040.html SH7040, SH7041, SH7042, SH7043, SH7044, SH7045], Renesas}} for a combined rating of 74.45464 MIPS (MIPS however, is not a true indication of processor performance in many cases). Each SH2 comes with an internal 4 [[Byte|KB]] [[RAM]] cache in order to speed up processing tasks.
+The [[Sega Saturn]] is powered by two SH-2 processors running in a Master/Slave configuration. These particular SH-2 chips run at 28.6364 MHz (versions were developed which ran as high as 40 MHz), and are capable of processing up to 37.227268 MIPS each (1.3 MIPS per MHz),{{fileref|SH-2A.pdf|page=2}}{{ref|[https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/superh/sh7040/sh7040.html SH7040, SH7041, SH7042, SH7043, SH7044, SH7045], Renesas}} for a combined rating of 74.45464 MIPS (MIPS however, is not a true indication of processor performance in many cases). Each SH-2 comes with an internal 4 [[Byte|KB]] [[RAM]] cache in order to speed up processing tasks.
-"The SH2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles." — ''Next Generation''
+{{Quote|
+The SH-2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles.
+|Next Generation
+|ref={{magref|nextgeneration|2|42}}}}
 ==Technical specifications==
@@ Line 21: / Line 24: @@
 :* 2x DIVU division units: 16/32/64-bit division,{{fileref|SH7604 Hardware Manual.pdf|page=303}} 1,468,531 divides/sec{{ref|39 cycles per divide{{fileref|Hitachi SuperH Programming Manual.pdf|page=155}}|group=fn}}
 * [[wikipedia:Bus (computing)|Bus]] width: 64‑bit (2× 32‑bit) internal, 32‑bit external{{fileref|ST-103-R1-040194.pdf}}
-* Word length: [[32-bit era|32-bit]]
+* Word length: 32-bit
 * Supports [[wikipedia:Master/slave (technology)|Master/Slave]] configuration with dual SH-2