Difference between revisions of "Sega NAOMI 2"

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Sega NAOMI 2

Manufacturer: Sega

Variants: Sega NAOMI 2 GD-ROM, Sega NAOMI 2 Satellite Terminal

Add-ons: GD-ROM

Release	Date	RRP	Code

The Sega NAOMI 2 is an arcade board developed by Sega and is a successor to Sega NAOMI hardware. It was originally released in 2000. Since it uses similar NAOMI architecture (but significantly beefed up), it is also fully backwards compatible with its predecessor.

The NAOMI 2 is significantly more powerful than the NAOMI, including a dual CPU setup, new T&L GPU, dual rasterizer GPU, increased memory, and faster clock rates and bandwidth. This leads to games with much more polygons than a NAOMI game, rendered at much faster speeds, while the new T&L GPU adds advanced lighting and particle effects. It was also more affordable than the very expensive (and difficult to program) Sega Hikaru arcade system that preceded it.^[1]

As with the NAOMI, the NAOMI 2 was also available in GD-ROM and Satellite Terminal variants. It was Sega's last proprietary arcade system board; subsequent Sega arcade boards have been based on console and PC hardware.

Development

VideoLogic's Elan, the T&L geometry GPU coprocessor used in the NAOMI 2, had been in development since 1998, when the original NAOMI arcade system and Dreamcast console launched.^[2] Yu Suzuki was involved in its development, insisting that it must have enough power to sustain in-game performance of at least 10 million polygons per second will all effects enabled.^[3]

Technical Specifications

NAOMI 2 Specifications

Main CPU: Hitachi SH‑4^[4] @ 200 MHz^[5]^[6]
- Units: 128‑bit SIMD vector units with graphic functions, 2× 64‑bit floating‑point units, 2× 32‑bit fixed‑point units
- Bus width: 128‑bit 64‑bit external
- Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
- Fixed‑point performance: 360 MIPS
- SH‑4 floating‑point performance: 1.4 GFLOPS
- Note: With Elan used as geometry coprocessor, the SH‑4's 128‑bit SIMD matrix unit can be dedicated to game physics, artificial intelligence, collision detection, overall game code, or further enhancing graphics. CPU load is reduced by 90% with Elan.^[7]
Sound engine: Yamaha AICA Super Intelligent Sound Processor @ 67 MHz
- Internal CPU: 32‑bit ARM7 RISC CPU @ 45 MHz
- CPU performance: 17 MIPS
- PCM/ADPCM: 16‑bit depth, 48 kHz sampling rate (DVD quality), 128 channels
- Other features: DSP, sound synthesizer
PLD: 4 PLD^{[n 1]}
- Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz^{[n 2]}
- Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6 MHz^{[n 3]}
- Sega 315‑6268 (Altera EPM7032AELC44‑10) CPLD @ 103.1 MHz^{[n 4]}
- Sega 315‑6269 (Altera MAX EPM7064AETC100‑10) CPLD @ 100 MHz^{[n 5]}
Operating systems:
- Sega native operating system
- Custom Windows CE, with DirectX 6.0, Direct3D and OpenGL support
Storage media: ROM cartridge
Extensions: communication, 4‑channel surround sound, PCI, MIDI, RS‑232C
Connection: JAMMA Video compliant

Graphics

GPU: 6 core processors (Elan, SH‑4 SIMD, 2× PowerVR2, 2 DAC)
- Core units: 15 units (Elan, 2× SH‑4 SIMD, 10 PowerVR2 cores, 2 DAC)
- Clock rate: 200 MHz
GPU T&L geometry coprocessor: VideoLogic Elan @ 100 MHz
- Bus width: 512‑bit (4× 128‑bit)^[11]
- Lighting: Up to 16 light sources per polygon, ambient lighting, parallel lighting, point lighting, spotlight lighting
- Vertex support: Combined dynamic and static model processing
- Features: Reduces CPU load to 1/10th (90% reduction), multiple light type support (ambient, parallel, point, spot), hardware Z clipping, offscreen & backface culling^[7]
- Elan floating‑point performance: 7.5 GFLOPS^[12]^{[n 6]}
GPU rasterizers: 2× NEC‑VideoLogic PowerVR2 @ 200 MHz^[12]
- Revision: Scaled with higher clock rate and more PE elements in ISP core, raised polygon performance^[13]
- Bus width: 128‑bit (2× 64‑bit)
- Cores: Tile Accelerator (TA), Image Synthesis Processor (ISP), Texture & Shading Processor (TSP), RAMDAC
- RAMDAC: 230 MHz
- Effects: Bump mapping, multi‑texturing, fog, alpha blending, mipmapping, bilinear filtering, trilinear filtering, anti‑aliasing, environment mapping, specular effects,^[14]^[15] normal mapping
- Features: Tiled rendering, deferred rendering, back‑face culling, hidden surface removal
- Defails: See NAOMI Specifications and Dreamcast Specifications for more details on PowerVR2 graphics system.
Video DAC: 2× Rohm BU1426KS @ 35.4695 MHz^[16]
- Bus width: 48‑bit (2× 24‑bit)
Color depth: 32‑bit ARGB, 16,777,216 colors (24‑bit color) with 8‑bit (256 levels) alpha blending, YUV and RGB color spaces, color key overlay^[17]
Display resolution: 31 kHz horizontal sync, 60 Hz refresh rate, JAMMA/VGA,^[18] progressive scan
- Single monitor: 496×384 to 800×608 pixels^[19]
- Dual monitor: 992×768 to 1600×608 pixels
Rendering fillrate:
- 12 GPixels/s: Opaque polygons^{[n 7]}
- 2 GPixels/s: Opaque and translucent polygons^[5]
Texture fillrate:
- 12 GTexels/s: Opaque polygons
- 2 GTexels/s: Opaque and translucent polygons
Textures per pass: 10 texture layers^[12]
T&L geometry: 8.7 GFLOPS^{[n 8]}
- Matrix transformations: 240 million vertices/sec^{[n 9]}
- Perspective transformations: 210 million vertices/sec^{[n 10]}
- 1 light source: 110 million vertices/sec^{[n 11]}
- 4 light sources: 26 million vertices/sec^{[n 12]}
- 6 light sources: 18 million vertices/sec^{[n 13]}
Polygon rendering:
- 100 million polygons/sec:^[12] 1 light source, flat shading, opaque polygons
- 10 million polygons/sec: 6 light sources, texture mapping, Gouraud shading, opaque/translucent polygons

Memory

Overall memory: 304–584 MB (136 MB RAM, 168–448 MB ROM)
- Video memory: 240–352 MB (96 MB RAM, 144–256 MB ROM)
Internal processor cache: 381.576 KB^{[n 14]}^[28]
- SH4 CPU cache: 281.564 KB^{[n 15]}
- PowerVR2 GPU cache: 67.5 KB^{[n 16]}
- AICA audio cache: 32.011 KB^{[n 17]}
- I/O Board MCU: 16.5 KB^{[n 18]}
System RAM: 136 MB^[4]
- Main RAM: 32 MB SDRAM
- VRAM: 96 MB
  - Elan: 32 MB SDRAM (geometry/model data)
  - PowerVR2: 64 MB SDRAM^{[n 19]}
- Sound RAM: 8 MB
- FPGA Configuration: 8 KB SRAM^[4]^[9]
- Backup SRAM: 32 KB^[30]
System ROM: 2048.25 KB^{[n 20]}
Cartridge ROM: 168–448 MB
- 2000 format: 168–280 MB^{[n 21]}
- 2005 format: Up to 448 MB^{[n 22]}

Bandwidth

Internal processor cache bandwidth:
- SH4 cache: 3.2 GB/s^{[n 23]}
- GPU cache:
  - Elan: 6.4 GB/s^{[n 24]}
  - PowerVR2: 62.4 GB/s^{[n 25]}
  - DAC: 213 MB/s^{[n 26]}
- AICA: 256 MB/s^{[n 27]}
- PLD: 9.3 GB/s^{[n 28]}
RAM/ROM memory bandwidth: 16.1 GB/s (15.1 GB/s system, 1 GB/s cartridge)
- Video memory: 14.01 GB/s (13.01 GB/s VRAM, 900 MB/s ROM)
System RAM bandwidth: 10 GB/s^[4]
- Main RAM: 1.6 GB/s^{[n 29]}
- VRAM: 8.4 GB/s
  - Elan: 6.4 GB/s^{[n 30]}
  - PowerVR2: 2 GB/s^{[n 31]}
- Sound RAM: 132 MB/s^{[n 32]}
- Backup SRAM: 44 MB/s^{[n 33]}
- FPGA Configuration: 6 MB/s^{[n 34]}
System ROM bandwidth: 88 MB/s^[4]
- BIOS EPROM: 80 MB/s^{[n 35]}
- EEPROM: 8 MB/s^{[n 36]}
Cartridge ROM bandwidth: 900 MB/s^{[n 37]}
- Note: High‑speed access allows ROM to effectively be used as RAM, and textures streamed directly from ROM.^[41]
Cartridge RAM bandwidth: 100 MB/s^{[n 38]}

NAOMI 2 GD-ROM Specifications

The NAOMI GD‑ROM, released in 2001, is identical to the standard NAOMI, but uses GD‑ROM discs for storage instead of ROM cartridges. It comes with a DIMM Board, which is very similar to a ROM cartridge, but with RAM instead of ROM. When a game is installed, the GD‑ROM content is loaded onto the DIMM Board RAM, so that the game data runs from the DIMM Board rather than the GD‑ROM disc. The NAOMI 2 GD‑ROM specification includes the following differences:

Board composition: Motherboard + Daughter Board + DIMM Board
Storage media: GD‑ROM drive
- GD‑ROM transfer rate: 1.8 MB/s (1800 KB/sec)

Memory

RAM: 392–648 MB (SDRAM)
- Main RAM: 32 MB
- VRAM: 96 MB
- Sound RAM: 8 MB
- DIMM RAM: 256–512 MB^[42]
L2 cache: 256 KB
ROM: 26 MB
- System ROM: 2048.25 KB^{[n 39]}
- DIMM ROM: 24 MB (EPROM)

Bandwidth

RAM bandwidth: 11–12 GB/s
- Main RAM: 1.6 GB/s
- VRAM: 8.4 GB/s
- Sound RAM: 132 MB/s
- SRAM: 44 MB/s
- DIMM RAM: 1.1–2.13 GB/s^{[n 40]}

List of Games

Notes

↑ [49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[4] 49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[4]]
↑ [42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[8] 5.3 GB/s 42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[8] 5.3 GB/s]
↑ [8‑bit,^[9] 6 MB/s 8‑bit,^[9] 6 MB/s]
↑ [2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[10] 1.3403 GB/s 2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[10] 1.3403 GB/s]
↑ [4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[10] 2.6 GB/s 4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[10] 2.6 GB/s]
↑ [75 floating-point operations per cycle 75 floating-point operations per cycle]
↑ [32 pixels per cycle^[20] 32 pixels per cycle^[20]]
↑ [Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS) Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS)]
↑ [Elan: 200 million vertices/sec (28 FLOPS per transform,^[21] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[22] Elan: 200 million vertices/sec (28 FLOPS per transform,^[21] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[22]]
↑ [Elan: 200 million vertices/sec, 31 FLOPS per vertex (28 FLOPS matrix transform,^[21] 3 FLOPS perspective division),^[23] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[22] 5 cycles perspective division),^[23] 12 cycles division latency^[24] Elan: 200 million vertices/sec, 31 FLOPS per vertex (28 FLOPS matrix transform,^[21] 3 FLOPS perspective division),^[23] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[22] 5 cycles perspective division),^[23] 12 cycles division latency^[24]]
↑ [Elan: 100 million vertices/sec (63 FLOPS per vertex,^[25] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[26]^[27] Elan: 100 million vertices/sec (63 FLOPS per vertex,^[25] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[26]^[27]]
↑ [Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
↑ [Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
↑ [390,734 bytes 390,734 bytes]
↑ [288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[12] 288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[12]]
↑ [69,120 bytes: 16.5 KB register memory, 24.5 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer 69,120 bytes: 16.5 KB register memory, 24.5 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer]
↑ [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]
↑ [512 bytes RAM, 16 KB ROM^[29] 512 bytes RAM, 16 KB ROM^[29]]
↑ [2× 32 MB 2× 32 MB]
↑ [2 MB BIOS EPROM, 256 bytes EEPROM^[4] 2 MB BIOS EPROM, 256 bytes EEPROM^[4]]
↑ [24 MB EPROM,^[31] 144–256 MB FlashROM/MROM 24 MB EPROM,^[31] 144–256 MB FlashROM/MROM]
↑ [128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[32] 128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[32]]
↑ [128‑bit, 200 MHz 128‑bit, 200 MHz]
↑ [512‑bit, 100 MHz 512‑bit, 100 MHz]
↑ [2x 1248‑bit, 200 MHz: 32-bit TA tile buffer,^[33] 32-bit ISP registers, 32-bit TSP registers,^[34] 1024-bit ISP PE Array,^[13] 64-bit TSP Texture Cache,^[20] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer 2x 1248‑bit, 200 MHz: 32-bit TA tile buffer,^[33] 32-bit ISP registers, 32-bit TSP registers,^[34] 1024-bit ISP PE Array,^[13] 64-bit TSP Texture Cache,^[20] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer]
↑ [48‑bit, 35.4695 MHz 48‑bit, 35.4695 MHz]
↑ [32‑bit, 67 MHz 32‑bit, 67 MHz]
↑ [656‑bit, 125 MHz 656‑bit, 125 MHz]
↑ [128‑bit, 100 MHz^[35] 128‑bit, 100 MHz^[35]]
↑ [512‑bit, 100 MHz^[11] 512‑bit, 100 MHz^[11]]
↑ [128‑bit, 125 MHz^[36] 128‑bit, 125 MHz^[36]]
↑ [16‑bit, 66 MHz 16‑bit, 66 MHz]
↑ [16‑bit, 22 MHz^[30] 16‑bit, 22 MHz^[30]]
↑ [8‑bit, 6 MHz^[9] 8‑bit, 6 MHz^[9]]
↑ [16‑bit, 40 MHz^[37]^[38] 16‑bit, 40 MHz^[37]^[38]]
↑ [2× 16‑bit, 2 MHz^[39] 2× 16‑bit, 2 MHz^[39]]
↑ [50 MHz^[40] 50 MHz^[40]]
↑ [16‑bit, 50 MHz 16‑bit, 50 MHz]
↑ [24 MB BIOS EPROM, 256 bytes EEPROM 24 MB BIOS EPROM, 256 bytes EEPROM]
↑ [1/2× 64‑bit, 133 MHz^[43]^[44] 1/2× 64‑bit, 133 MHz^[43]^[44]]

References

Sega arcade boards
Originating in arcades
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 VIC Dual G80 Zaxxon VCO Object System 1 LaserDisc Appoooh Hang-On System 2 System 16 OutRun Gigas X Board Y Board System 24 System 18 System 32 Model 1 Model 2 H1 Board Model 3
Console-based hardware
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SG-1000 System E System C Mega-Tech System Mega Play Sega Titan Video NAOMI Hikaru NAOMI 2 Atomiswave System SP Chihiro Triforce
PC-based hardware
05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Lindbergh Europa-R RingEdge RingWide RingEdge 2 Nu Nu 1.1 Nu 2 ALLS

[49.26nbsp.3Bunits.2C_656.E2.80.91bit_internal.2C_224.E2.80.91bit_external.2C_125.26nbsp.3BMHz.2C_9.25.26nbsp.3BGB.2Fs.7F.27.22.60UNIQ--ref-00000012-QINU.60.22.27.7F-8] [49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[4] 49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[4]]

[42.26nbsp.3Bunits.2C_336.E2.80.91bit_.2842.C3.97.26nbsp.3B8.E2.80.91bit.29_internal.2C_120.E2.80.91bit_external.2C.7F.27.22.60UNIQ--ref-00000016-QINU.60.22.27.7F_5.3.26nbsp.3BGB.2Fs-10] [42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[8] 5.3 GB/s 42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[8] 5.3 GB/s]

[8.E2.80.91bit.2C.7F.27.22.60UNIQ--ref-0000001A-QINU.60.22.27.7F_6.26nbsp.3BMB.2Fs-12] [8‑bit,^[9] 6 MB/s 8‑bit,^[9] 6 MB/s]

[2.26nbsp.3Bunits.2C_104.E2.80.91bit_.282.C3.97.26nbsp.3B52.E2.80.91bit.29_internal.2C_32.E2.80.91bit_.282.C3.97.26nbsp.3B16.E2.80.91bit.29_external.2C.7F.27.22.60UNIQ--ref-0000001E-QINU.60.22.27.7F_1.3403.26nbsp.3BGB.2Fs-14] [2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[10] 1.3403 GB/s 2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[10] 1.3403 GB/s]

[4.26nbsp.3Bunits.2C_208.E2.80.91bit_.284.C3.97.26nbsp.3B52.E2.80.91bit.29_internal.2C_64.E2.80.91bit_.284.C3.97.26nbsp.3B16.E2.80.91bit.29_external.2C.7F.27.22.60UNIQ--ref-00000022-QINU.60.22.27.7F_2.6.26nbsp.3BGB.2Fs-15] [4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[10] 2.6 GB/s 4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[10] 2.6 GB/s]

[75_floating-point_operations_per_cycle-18] [75 floating-point operations per cycle 75 floating-point operations per cycle]

[32_pixels_per_cycle.7F.27.22.60UNIQ--ref-0000003A-QINU.60.22.27.7F-27] [32 pixels per cycle^[20] 32 pixels per cycle^[20]]

[Elan:_7.5_GFLOPS_.2875_floating-point_operations_per_cycle.29_.3Cbr.3E_SH.E2.80.914_SIMD:_180_MHz_available_.2810.25_load.2C_20_MHz_used.29.2C_1.26_GFLOPS_.2890.25_of_1.4_GFLOPS.29-28] [Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS) Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS)]

[Elan:_200_million_vertices.2Fsec_.2828_FLOPS_per_transform.2C.7F.27.22.60UNIQ--ref-00000041-QINU.60.22.27.7F_2_transforms_per_cycle.29_.3Cbr.3E_SH-4:_45_million_vertices.2Fsec_.284_cycles_per_transform.29.7F.27.22.60UNIQ--ref-00000044-QINU.60.22.27.7F-31] [Elan: 200 million vertices/sec (28 FLOPS per transform,^[21] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[22] Elan: 200 million vertices/sec (28 FLOPS per transform,^[21] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[22]]

[Elan:_200_million_vertices.2Fsec.2C_31_FLOPS_per_vertex_.2828_FLOPS_matrix_transform.2C.7F.27.22.60UNIQ--ref-00000046-QINU.60.22.27.7F_3_FLOPS_perspective_division.29.2C.7F.27.22.60UNIQ--ref-00000047-QINU.60.22.27.7F_2_transforms_per_cycle_.3Cbr.3E_SH-4:_15_million_vertices.2Fsec.2C_12_cycles_per_vertex_.284_cycles_matrix_transform.2C.7F.27.22.60UNIQ--ref-0000004A-QINU.60.22.27.7F_5_cycles_perspective_division.29.2C.7F.27.22.60UNIQ--ref-0000004B-QINU.60.22.27.7F_12_cycles_division_latency.7F.27.22.60UNIQ--ref-0000004E-QINU.60.22.27.7F-34] [Elan: 200 million vertices/sec, 31 FLOPS per vertex (28 FLOPS matrix transform,^[21] 3 FLOPS perspective division),^[23] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[22] 5 cycles perspective division),^[23] 12 cycles division latency^[24] Elan: 200 million vertices/sec, 31 FLOPS per vertex (28 FLOPS matrix transform,^[21] 3 FLOPS perspective division),^[23] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[22] 5 cycles perspective division),^[23] 12 cycles division latency^[24]]

[Elan:_100_million_vertices.2Fsec_.2863_FLOPS_per_vertex.2C.7F.27.22.60UNIQ--ref-00000050-QINU.60.22.27.7F_1_vertex_per_cycle.29_.3Cbr.3E_SH-4:_12_million_vertices.2Fsec.2C_14_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_surface_normal.2C_4_cycles_lighting_matrix.29.7F.27.22.60UNIQ--ref-00000053-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000056-QINU.60.22.27.7F-38] [Elan: 100 million vertices/sec (63 FLOPS per vertex,^[25] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[26]^[27] Elan: 100 million vertices/sec (63 FLOPS per vertex,^[25] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[26]^[27]]

[Elan:_20_million_vertices.2Fsec.2C_5_cycles_per_vertex_.281_cycle_transform.2C_1_cycle_per_light_source.29_.3Cbr.3E_SH-4:_6_million_vertices.2Fsec.2C_29_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_per_surface_normal.2C_4_cycles_per_lighting_matrix.29-39] [Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]

[Elan:_14_million_vertices.2Fsec.2C_7_cycles_per_vertex_.281_cycle_transform.2C_1_cycle_per_light_source.29_.3Cbr.3E_SH-4:_4_million_vertices.2Fsec.2C_39_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_per_surface_normal.2C_4_cycles_per_lighting_matrix.29-40] [Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]

[390.2C734_.5B.5Bbyte.5D.5Ds-41] [390,734 bytes 390,734 bytes]

[288.2C322_bytes:_8_KB_instruction_cache.2C_16_KB_data_cache.2C_64_bytes_store_queue_cache.2C_1538_bytes_registers.2C_256.26nbsp.3BKB_.5B.5Bwikipedia:L2_cache.7CL2_cache.5D.5D.7F.27.22.60UNIQ--ref-0000005F-QINU.60.22.27.7F-43] [288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[12] 288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[12]]

[69.2C120_bytes:_16.5_KB_register_memory.2C_24.5_KB_ISP_cache.2C_26_KB_TSP_cache.2C_512_bytes_FIFO_buffer-44] [69,120 bytes: 16.5 KB register memory, 24.5 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer 69,120 bytes: 16.5 KB register memory, 24.5 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer]

[32.2C780_bytes:_32_KB_sound_registers.2C_8_bytes_RTC_registers.2C_4_bytes_FIFO_buffer-45] [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]

[512.26nbsp.3Bbytes_RAM.2C_16.26nbsp.3BKB_ROM.7F.27.22.60UNIQ--ref-00000065-QINU.60.22.27.7F-47] [512 bytes RAM, 16 KB ROM^[29] 512 bytes RAM, 16 KB ROM^[29]]

[2.C3.97.26nbsp.3B32.26nbsp.3BMB-48] [2× 32 MB 2× 32 MB]

[2.26nbsp.3BMB_.5B.5BBIOS.5D.5D_.5B.5BEPROM.5D.5D.2C_256.26nbsp.3Bbytes_.5B.5BEPROM.7CEEPROM.5D.5D.7F.27.22.60UNIQ--ref-00000070-QINU.60.22.27.7F-50] [2 MB BIOS EPROM, 256 bytes EEPROM^[4] 2 MB BIOS EPROM, 256 bytes EEPROM^[4]]

[24.26nbsp.3BMB_.5B.5BEPROM.5D.5D.2C.7F.27.22.60UNIQ--ref-00000072-QINU.60.22.27.7F_144.E2.80.93256_MB_.5B.5Bwikipedia:FlashROM.7CFlashROM.5D.5D.2F.5B.5Bwikipedia:Mask_ROM.7CMROM.5D.5D-52] [24 MB EPROM,^[31] 144–256 MB FlashROM/MROM 24 MB EPROM,^[31] 144–256 MB FlashROM/MROM]

[128.E2.80.93448.26nbsp.3BMB_FlashROM.2C_0.E2.80.9340.26nbsp.3BMB_EPROM.2C_128.26nbsp.3BKB_Flash_.5B.5Bwikipedia:Programmable_read-only_memory.7CPROM.5D.5D.7F.27.22.60UNIQ--ref-00000076-QINU.60.22.27.7F-54] [128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[32] 128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[32]]

[128.E2.80.91bit.2C_200.26nbsp.3BMHz-55] [128‑bit, 200 MHz 128‑bit, 200 MHz]

[512.E2.80.91bit.2C_100.26nbsp.3BMHz-56] [512‑bit, 100 MHz 512‑bit, 100 MHz]

[2x_1248.E2.80.91bit.2C_200_MHz:_32-bit_TA_tile_buffer.2C.7F.27.22.60UNIQ--ref-0000007C-QINU.60.22.27.7F_32-bit_ISP_registers.2C_32-bit_TSP_registers.2C.7F.27.22.60UNIQ--ref-0000007D-QINU.60.22.27.7F_1024-bit_ISP_PE_Array.2C.7F.27.22.60UNIQ--ref-00000080-QINU.60.22.27.7F_64-bit_TSP_Texture_Cache.2C.7F.27.22.60UNIQ--ref-00000083-QINU.60.22.27.7F_32-bit_TSP_Tile_Accumulation_Buffer.2C_32-bit_Secondary_Accumulation_Buffer-59] [2x 1248‑bit, 200 MHz: 32-bit TA tile buffer,^[33] 32-bit ISP registers, 32-bit TSP registers,^[34] 1024-bit ISP PE Array,^[13] 64-bit TSP Texture Cache,^[20] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer 2x 1248‑bit, 200 MHz: 32-bit TA tile buffer,^[33] 32-bit ISP registers, 32-bit TSP registers,^[34] 1024-bit ISP PE Array,^[13] 64-bit TSP Texture Cache,^[20] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer]

[48.E2.80.91bit.2C_35.4695.26nbsp.3BMHz-60] [48‑bit, 35.4695 MHz 48‑bit, 35.4695 MHz]

[32.E2.80.91bit.2C_67.26nbsp.3BMHz-61] [32‑bit, 67 MHz 32‑bit, 67 MHz]

[656.E2.80.91bit.2C_125.26nbsp.3BMHz-62] [656‑bit, 125 MHz 656‑bit, 125 MHz]

[128.E2.80.91bit.2C_100.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-0000008B-QINU.60.22.27.7F-64] [128‑bit, 100 MHz^[35] 128‑bit, 100 MHz^[35]]

[512.E2.80.91bit.2C_100.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-0000008F-QINU.60.22.27.7F-65] [512‑bit, 100 MHz^[11] 512‑bit, 100 MHz^[11]]

[128.E2.80.91bit.2C_125.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-00000093-QINU.60.22.27.7F-67] [128‑bit, 125 MHz^[36] 128‑bit, 125 MHz^[36]]

[16.E2.80.91bit.2C_66.26nbsp.3BMHz-68] [16‑bit, 66 MHz 16‑bit, 66 MHz]

[16.E2.80.91bit.2C_22.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-00000098-QINU.60.22.27.7F-69] [16‑bit, 22 MHz^[30] 16‑bit, 22 MHz^[30]]

[8.E2.80.91bit.2C_6.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-0000009C-QINU.60.22.27.7F-70] [8‑bit, 6 MHz^[9] 8‑bit, 6 MHz^[9]]

[16.E2.80.91bit.2C_40.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000A1-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000A4-QINU.60.22.27.7F-73] [16‑bit, 40 MHz^[37]^[38] 16‑bit, 40 MHz^[37]^[38]]

[2.C3.97.26nbsp.3B16.E2.80.91bit.2C_2.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000A8-QINU.60.22.27.7F-75] [2× 16‑bit, 2 MHz^[39] 2× 16‑bit, 2 MHz^[39]]

[50.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000AC-QINU.60.22.27.7F-77] [50 MHz^[40] 50 MHz^[40]]

[16.E2.80.91bit.2C_50.26nbsp.3BMHz-79] [16‑bit, 50 MHz 16‑bit, 50 MHz]

[24.26nbsp.3BMB_BIOS_EPROM.2C_256.26nbsp.3Bbytes_EEPROM-81] [24 MB BIOS EPROM, 256 bytes EEPROM 24 MB BIOS EPROM, 256 bytes EEPROM]

[1.2F2.C3.97.26nbsp.3B64.E2.80.91bit.2C_133.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000B2-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000B5-QINU.60.22.27.7F-84] [1/2× 64‑bit, 133 MHz^[43]^[44] 1/2× 64‑bit, 133 MHz^[43]^[44]]

[:File:NextGeneration_US_76.pdf_p37-1] File:NextGeneration US 76.pdf, page 37

[.5Bhttps:.2F.2Fweb.archive.org.2Fweb.2F19981206111041.2Fwww.techweb.com.2Fwire.2Fstory.2FTWB19980923S0008_NEC_Introduces_PowerVR_3-D_Engine_.2809.2F23.2F98.29.5D-2] NEC Introduces PowerVR 3-D Engine (09/23/98) (Wayback Machine: 1998-12-06 11:10)

[:File:NextGeneration_US_77.pdf_p61-3] File:NextGeneration US 77.pdf, page 61

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fnaomi.cpp_Sega_NAOMI_.2F_NAOMI_2_.28MAME.29.5D-4] 4.0 ^4.1 ^4.2 ^4.3 ^4.4 ^4.5 ^4.6 Sega NAOMI / NAOMI 2 (MAME)

[:File:DCUK_16.pdf_p41-5] 5.0 ^5.1 File:DCUK 16.pdf, page 41

[:File:SH-4_Software_Manual.pdf_p-6] File:SH-4 Software Manual.pdf

[Press_release:_2000-09-21:_Sega_Announces_NAOMI2_Next_Generation_Arcade_Systems_Using_Imagination_Technologies.E2.80.99_PowerVR_Graphics_Architecture-7] 7.0 ^7.1 Press release: 2000-09-21: Sega Announces NAOMI2 Next Generation Arcade Systems Using Imagination Technologies’ PowerVR Graphics Architecture

[:File:EPF8452A_datasheet.pdf_p-9] File:EPF8452A datasheet.pdf

[:File:EPC1064_datasheet.pdf_p-11] 9.0 ^9.1 ^9.2 File:EPC1064 datasheet.pdf

[:File:EPM7032AE_datasheet.pdf_p-13] 10.0 ^10.1 File:EPM7032AE datasheet.pdf

[:File:UPD4564323_datasheet.pdf_p-16] 11.0 ^11.1 File:UPD4564323 datasheet.pdf

[.5Bhttp:.2F.2Fwww.ign.com.2Fboards.2Fthreads.2Fnoami-2-future.6157195.2F_NAOMI_2_Specifications_.28May_31.2C_2001.29.5D-17] 12.0 ^12.1 ^12.2 ^12.3 ^12.4 NAOMI 2 Specifications (May 31, 2001)

[:File:PowerVR.pdf_p3-19] 13.0 ^13.1 File:PowerVR.pdf, page 3

[.5Bhttp:.2F.2Fign.com.2Farticles.2F2000.2F09.2F21.2Fjamma-2000-naomi-2-revealed_JAMMA_2000:_NAOMI_2_Revealed_.28September_20.2C_2000.29.5D-20] JAMMA 2000: NAOMI 2 Revealed (September 20, 2000)

[:File:NAOMI_1998_Press_Release_JP.pdf_p-21] File:NAOMI 1998 Press Release JP.pdf

[:File:BU142_datasheet.pdf_p-22] File:BU142 datasheet.pdf

[.5Bhttp:.2F.2Fweb.archive.org.2Fweb.2F20070811102018.2Fhttp:.2F.2Fwww3.sharkyextreme.com.2Fhardware.2Freviews.2Fvideo.2Fneon250.2F2.shtml_Neon_250_Specs_.26_Features.5D-23] Neon 250 Specs & Features (Wayback Machine: 2007-08-11 10:20)

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_Universal_Sega_Naomi_Universal.5D-24] Sega Naomi Universal

[.5Bhttp:.2F.2Fcadcdev.sourceforge.net.2Fdocs.2Fkos-current.2Fvideo_8h_source.html_Dreamcast_Video_.28KallistiOS.29.5D-25] Dreamcast Video (KallistiOS)

[:File:DreamcastDevBoxSystemArchitecture.pdf_p96-26] 20.0 ^20.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 96

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA95_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28page_95.29.5D-29] 21.0 ^21.1 Design of Digital Systems and Devices (page 95)

[:File:SH-4_Next-Generation_DSP_Architecture.pdf_p12-30] 22.0 ^22.1 File:SH-4 Next-Generation DSP Architecture.pdf, page 12

[.5Bhttp:.2F.2Fgamedev.allusion.net.2Fdocs.2Fkos-current.2Fmatrix_8h.html_Dreamcast:_Basic_matrix_operations_.28KallistiOS.29.5D-32] 23.0 ^23.1 Dreamcast: Basic matrix operations (KallistiOS)

[:File:SH-4_Software_Manual.pdf_p211-33] File:SH-4 Software Manual.pdf, page 211

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA96_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28page_96.29.5D-35] Design of Digital Systems and Devices (page 96)

[:File:SH-4_Software_Manual.pdf_p151-36] File:SH-4 Software Manual.pdf, page 151

[:File:SH-4_Next-Generation_DSP_Architecture.pdf_p31-37] File:SH-4 Next-Generation DSP Architecture.pdf, page 31

[:File:DreamcastDevBoxSystemArchitecture.pdf_p-42] File:DreamcastDevBoxSystemArchitecture.pdf

[:File:TMP90PH44_datasheet.pdf_p-46] File:TMP90PH44 datasheet.pdf

[:File:HM62256B_datasheet.pdf_p-49] 30.0 ^30.1 File:HM62256B datasheet.pdf

[.5Bhttp:.2F.2Fmamedb.com.2Fgame.2Fclubkrte_Club_Kart:_European_Session_.28MAME.29.5D-51] Club Kart: European Session (MAME)

[:File:XCF01S_datasheet.pdf_p-53] File:XCF01S datasheet.pdf

[:File:DreamcastDevBoxSystemArchitecture.pdf_p165-57] File:DreamcastDevBoxSystemArchitecture.pdf, page 165

[.5Bhttp:.2F.2Fmc.pp.se.2Fdc.2Fpvr.html_PowerVR_.28Dreamcast_Hardware.29.5D-58] PowerVR (Dreamcast Hardware)

[:File:HM5264_datasheet.pdf_p-63] File:HM5264 datasheet.pdf

[:File:HY57V161610D_datasheet.pdf_p-66] File:HY57V161610D datasheet.pdf

[:File:CY2292_datasheet.pdf_p-71] File:CY2292 datasheet.pdf

[:File:M27C160_datasheet.pdf_p-72] File:M27C160 datasheet.pdf

[:File:AT93C46_datasheet.pdf_p-74] File:AT93C46 datasheet.pdf

[:File:S29GL-N_datasheet.pdf_p-76] File:S29GL-N datasheet.pdf

[.5Bhttp:.2F.2Ffarm6.staticflickr.com.2F5471.2F12172411045_18bfc5912f_c.jpg_Hideki_Sato_Sega_Inteview_.28Edge.29.5D-78] Hideki Sato Sega Inteview (Edge)

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_DIMM_board_and_GD-ROM_Sega_NAOMI_DIMM_board_and_GD-ROM.5D-80] Sega NAOMI DIMM board and GD-ROM

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_DIMM_board_and_GD-ROM_Sega_Naomi_DIMM_board_and_GD-ROM.5D-82] Sega Naomi DIMM board and GD-ROM

[:File:M366S3323CT0_datasheet.pdf_p-83] File:M366S3323CT0 datasheet.pdf

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@@ Line 123: / Line 123: @@
 ** GPU cache:
 *** Elan: 6.4&nbsp;GB/s{{ref|512‑bit, 100&nbsp;MHz|group=n}}
-*** PowerVR2: 31.2&nbsp;GB/s{{ref|1248‑bit, 200&nbsp;MHz|group=n}}
+*** PowerVR2: 62.4&nbsp;GB/s{{ref|2x 1248‑bit, 200 MHz: 32-bit TA tile buffer,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=165}} 32-bit ISP registers, 32-bit TSP registers,{{ref|[http://mc.pp.se/dc/pvr.html PowerVR (Dreamcast Hardware)]}} 1024-bit ISP PE Array,{{fileref|PowerVR.pdf|page=3}} 64-bit TSP Texture Cache,{{fileref|DreamcastDevBoxSystemArchitecture.pdf|page=96}} 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer|group=n}}
 *** DAC: 213&nbsp;MB/s{{ref|48‑bit, 35.4695&nbsp;MHz|group=n}}
 ** AICA: 256&nbsp;MB/s{{ref|32‑bit, 67&nbsp;MHz|group=n}}

Difference between revisions of "Sega NAOMI 2"

From Sega Retro

Revision as of 18:26, 1 December 2016

Contents

Development

Technical Specifications

NAOMI 2 Specifications

Graphics

Memory

Bandwidth

NAOMI 2 GD-ROM Specifications

Memory

Bandwidth

List of Games

NAOMI 2 Games

NAOMI 2 GD-ROM Games

NAOMI 2 Satellite Terminal Games

Notes

References