Difference between revisions of "Sega Virtua Processor"

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#REDIRECT [[Mega Drive cartridges#Sega Virtua Processor]]
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[[File:SegaVirtuaProcessor logo.png|thumb|right]]
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{{stub}}The '''Sega Virtua Processor''' (SVP) is a custom-designed [[Sega Mega Drive]]-compatible DSP chip which allows for enhanced graphics and sound capabilities. This chip essentially serves as an extra processor, allowing games to produce a significantly higher number of polygons than would be possible on a standard Mega Drive. Primarily seen as a reaction to the [[Super Famicom]]'s [[wikipedia:Super FX|Super FX]] chip, the SVP boasted more performance than Nintendo's chip but would ultimately see use in only a single title - ''[[Virtua Racing]]'', which saw an increase in both its cartridge size and retail price.
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==History==
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[[File:SegaVirtuaProcessor JP chip.png|thumb|right]]
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The SVP chip was revealed for the [[Mega Drive]] in Summer 1993, before the Mega Drive version of ''[[Virtua Racing]]'' released in 1994.{{magref|cvg|150|50}} Interestingly, ''Virtua Racing'' was the first to showcase the power of the SVP chip - plans were underway to produce more games using this chip, using a "Modular Converter" cartridge to cut production costs. This converter would contain the SVP chip, with the enhanced game designed to use the SVP chip plugging into the top of the unit.{{magref|gamepro|57|160}} However, due to the costs of production against the Mega Drive/Genesis' age and falling popularity, the project was dropped. ''Virtua Racing'' also has a cartridge roughly one-and-a-half times the size of a usual Mega Drive cartridge due to the added chip, and is incompatible with the [[Sega 32X]] add-on.
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Early versions of ''[[Sonic the Hedgehog 3]]'' were planned to use the SVP chip to create three-dimensional playfields. With [[Yuji Naka]]'s interest in taking the franchise in new directions, the original plan was to use the chip to create an isometric world for [[sonic:Sonic the Hedgehog|Sonic]] to run in (a similar perspective to ''[[Sonic Labyrinth]]'' and ''[[Sonic 3D: Flickies' Island]]''), which would have resulted in a vastly different game. However, [[Sega of Japan]] refused [[Sonic Team]]'s demands for its inclusion, stating that the chip would not be ready by the game's original planned release date. Instead, the development team decided to create another traditional two-dimensional platformer.{{ref|https://info.sonicretro.org/Sonic_the_Hedgehog_3/Development}}
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While it has been assumed that the SVP was only intended for the Mega Drive, there are indications that Sega may have had greater plans for the chip. Third-party developer [[Artech Digital Entertainments]] once considered using the SVP in their ultimately-unreleased [[Sega VR]] title ''[[Outlaw Racing]]''{{ref|http://web.ncf.ca/au829/OutlawSprintCars/index.html}}, and the [[CRI]] title ''[[Zaxxon's Motherbase 2000]]'' contains remnants of unused SVP support - despite being a [[Sega 32X]] game.
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==Magazine articles==
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{{mainArticle|{{PAGENAME}}/Magazine articles}}
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==Technical specifications==
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The SVP chip adds the following capabilities to the Mega Drive hardware. For comparisons to Nintendo's [[wikipedia:Super FX|Super FX]] chip, see [[Blast processing|blast processing]].
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{{multicol|
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* GPU: [[Sega]] 315-5750{{intref|SVP Reference Guide (2008-02-06)}} ([[Samsung]] SSP1601) [[wikipedia:Digital signal processor|DSP]]{{intref|SVP documentation (2014-09-23)}}{{fileref|SSP1601 datasheet.pdf}} @ 23.01136 MHz{{intref|SVP Reference Guide (2008-02-06)}} (25 MIPS){{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}}{{fileref|SSP1601 datasheet.pdf}}
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:* DSP core: 16-bit fixed-point arithmetic, 32-bit output, 16-bit word size, 25 registers (8 general, 8 external, 8 pointer, 1 status)
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:* [[wikipedia:Arithmetic logic unit|ALU]]: 32-bit, status register
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:* Multiplier: 32-bit output, 16x16-bit pipelined multiplication
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* DSP buses: 6 buses{{fileref|SSP1601 datasheet.pdf}}
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:* 32-bit internal data buses: Data (D) bus (16-bit), subsidiary (S) bus (16-bit)
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:* 16-bit program data bus: Program data (PD) bus
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:* 16-bit external data bus: External (EXT) bus
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:* 16-bit address bus: Program address (PA) bus
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:* 32-bit arithmetic bus: Multiplier (M) bus
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* Audio: 2 [[wikipedia:Pulse-width modulation|PWM]] channels{{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}}
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}}
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=====Graphics=====
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{{multicol|
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* DSP performance:
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:* [[wikipedia:Multiply–accumulate operation|MAC operations]]: 1 MAC (multiply-accumulate) per cycle,{{fileref|SSP1601 datasheet.pdf}} 23.01136 million MACs per second
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:* Fixed-point calculations: 2 calculations (multiply and add) per cycle,{{intref|SVP documentation (2014-09-23)}} 46.02272 million calculations (23.01136 million multiplies, 23.01136 million adds) per second
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* Framebuffer: 320×192, double-buffered, 30 FPS, 60 KB (dual 30 KB) buffers in [[wikipedia:FPM DRAM|FPM DRAM]] (1.8432 MB/s, 1.8432 MHz DSP cycles), 30 KB buffer in Mega Drive [[VRAM]] (921.6 KB/s DMA transfer, equivalent to 2.7648 MHz DSP cycles), 4.608 MHz DSP cycles for framebuffer
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:* [[Fillrate]]: 18.181818 [[Pixel|MPixels/s]] (18.181818 MHz FPM DRAM){{ref|1=[http://tinyurl.com/ppdd95v Virtua Racing (Euro)]}}{{fileref|TC511664B datasheet.pdf}}
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* 3D polygon [[wikipedia:Transform and lighting|T&L]] geometry:
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:* Geometry transformations: 60,000 polygons/sec{{ref|1=369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA95 ''Design of Digital Systems and Devices'' (pages 95-97)]}} 32 cycles per divide|group=n}}
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:* Lighting calculations: 50,000 polygons/sec{{ref|1=390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA95 ''Design of Digital Systems and Devices'' (pages 95-97)]}} 32 cycles per divide|group=n}}
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* 3D polygon rendering:
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:* Flat shading:{{ref|18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,{{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA33 ''Algorithms for Parallel Polygon Rendering'' (pages 33-36)]}}{{ref|1=[http://sirkan.iit.bme.hu/~szirmay/abbas.pdf#page=53 Transformation Of Rendering Algorithms For Hardware Implementation (page 53)]}}{{intref|SVP Reference Guide (2008-02-06)}} 2 framebuffer access cycles), 2 cycles per pixel{{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA35 ''Algorithms for Parallel Polygon Rendering'' (page 35)]}}|group=n}} 20,000 polygons/sec (8×16 polygons),{{ref|724 cycles per polygon{{intref|SVP Register Guide (2008-02-06)}}|group=n}} 10,000 polygons/sec (16×32 polygons),{{ref|1492 cycles per polygon{{intref|SVP Register Guide (2008-02-06)}}|group=n}} 9000 polygons/sec (''[[Virtua Racing]]''){{ref|[http://www.ign.com/games/virtua-racing/gen-6398 Virtua Racing] ([[wikipedia:IGN|IGN]])}}
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:* Texture mapping: 3000 polygons/sec (8×16 texel textures){{ref|1=5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon)
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*258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access
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*4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel){{ref|1=[https://books.google.co.uk/books?id=teMHqC2BnuYC&pg=PA110 ''State of the Art in Computer Graphics: Visualization and Modeling'' (page 110)]}}|group=n}}
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}}
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=====Memory=====
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{{multicol|
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* Memory: 2179 KB (2.128 MB){{intref|SVP documentation (2014-09-23)}}
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:* RAM: 131 KB
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::* 128 KB [[wikipedia:FPM DRAM|FPM DRAM]]
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::* 1 KB [[SRAM]] cache{{fileref|SSP1601 datasheet.pdf}}
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::* 2 KB IRAM (instruction RAM) [[wikipedia:Cache (computing)|cache]]{{intref|SVP Reference Guide (2008-02-06)}}
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:* ROM: 2 MB (128 KB code, 1920 KB data){{intref|SVP Reference Guide (2008-02-06)}}
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* RAM bandwidth:
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:* FPM DRAM: 34.679066 MB/sec (16-bit, 18.181818 MHz, 55ns cycles, 80ns access){{ref|1=[http://tinyurl.com/ppdd95v Virtua Racing (Euro)]}}{{fileref|TC511664B datasheet.pdf}}
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:* SRAM cache: 92.04544 MB/sec (32-bit, dual 16-bit banks,{{fileref|SSP1601 datasheet.pdf}}{{intref|SVP Register Guide (2008-02-06)}} 23.01136 MHz, 43ns){{intref|SVP documentation (2014-09-23)}}{{fileref|SSP1601 datasheet.pdf}}
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}}
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==Notes==
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<references group="n"/>
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==References==
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<references/>

Latest revision as of 21:18, 7 August 2022

SegaVirtuaProcessor logo.png

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The Sega Virtua Processor (SVP) is a custom-designed Sega Mega Drive-compatible DSP chip which allows for enhanced graphics and sound capabilities. This chip essentially serves as an extra processor, allowing games to produce a significantly higher number of polygons than would be possible on a standard Mega Drive. Primarily seen as a reaction to the Super Famicom's Super FX chip, the SVP boasted more performance than Nintendo's chip but would ultimately see use in only a single title - Virtua Racing, which saw an increase in both its cartridge size and retail price.

History

SegaVirtuaProcessor JP chip.png

The SVP chip was revealed for the Mega Drive in Summer 1993, before the Mega Drive version of Virtua Racing released in 1994.[1] Interestingly, Virtua Racing was the first to showcase the power of the SVP chip - plans were underway to produce more games using this chip, using a "Modular Converter" cartridge to cut production costs. This converter would contain the SVP chip, with the enhanced game designed to use the SVP chip plugging into the top of the unit.[2] However, due to the costs of production against the Mega Drive/Genesis' age and falling popularity, the project was dropped. Virtua Racing also has a cartridge roughly one-and-a-half times the size of a usual Mega Drive cartridge due to the added chip, and is incompatible with the Sega 32X add-on.

Early versions of Sonic the Hedgehog 3 were planned to use the SVP chip to create three-dimensional playfields. With Yuji Naka's interest in taking the franchise in new directions, the original plan was to use the chip to create an isometric world for Sonic to run in (a similar perspective to Sonic Labyrinth and Sonic 3D: Flickies' Island), which would have resulted in a vastly different game. However, Sega of Japan refused Sonic Team's demands for its inclusion, stating that the chip would not be ready by the game's original planned release date. Instead, the development team decided to create another traditional two-dimensional platformer.[3]

While it has been assumed that the SVP was only intended for the Mega Drive, there are indications that Sega may have had greater plans for the chip. Third-party developer Artech Digital Entertainments once considered using the SVP in their ultimately-unreleased Sega VR title Outlaw Racing[4], and the CRI title Zaxxon's Motherbase 2000 contains remnants of unused SVP support - despite being a Sega 32X game.

Magazine articles

Main article: Sega Virtua Processor/Magazine articles.

Technical specifications

The SVP chip adds the following capabilities to the Mega Drive hardware. For comparisons to Nintendo's Super FX chip, see blast processing.

  • DSP core: 16-bit fixed-point arithmetic, 32-bit output, 16-bit word size, 25 registers (8 general, 8 external, 8 pointer, 1 status)
  • ALU: 32-bit, status register
  • Multiplier: 32-bit output, 16x16-bit pipelined multiplication
  • DSP buses: 6 buses[7]
  • 32-bit internal data buses: Data (D) bus (16-bit), subsidiary (S) bus (16-bit)
  • 16-bit program data bus: Program data (PD) bus
  • 16-bit external data bus: External (EXT) bus
  • 16-bit address bus: Program address (PA) bus
  • 32-bit arithmetic bus: Multiplier (M) bus
Graphics
  • DSP performance:
  • MAC operations: 1 MAC (multiply-accumulate) per cycle,[7] 23.01136 million MACs per second
  • Fixed-point calculations: 2 calculations (multiply and add) per cycle,[6] 46.02272 million calculations (23.01136 million multiplies, 23.01136 million adds) per second
  • Framebuffer: 320×192, double-buffered, 30 FPS, 60 KB (dual 30 KB) buffers in FPM DRAM (1.8432 MB/s, 1.8432 MHz DSP cycles), 30 KB buffer in Mega Drive VRAM (921.6 KB/s DMA transfer, equivalent to 2.7648 MHz DSP cycles), 4.608 MHz DSP cycles for framebuffer
  • 3D polygon T&L geometry:
  • Geometry transformations: 60,000 polygons/sec[n 1]
  • Lighting calculations: 50,000 polygons/sec[n 2]
  • 3D polygon rendering:
  • Flat shading:[n 3] 20,000 polygons/sec (8×16 polygons),[n 4] 10,000 polygons/sec (16×32 polygons),[n 5] 9000 polygons/sec (Virtua Racing)[16]
  • Texture mapping: 3000 polygons/sec (8×16 texel textures)[n 6]
Memory
  • Memory: 2179 KB (2.128 MB)[6]
  • RAM: 131 KB
  • ROM: 2 MB (128 KB code, 1920 KB data)[5]
  • RAM bandwidth:
  • FPM DRAM: 34.679066 MB/sec (16-bit, 18.181818 MHz, 55ns cycles, 80ns access)[9][10]
  • SRAM cache: 92.04544 MB/sec (32-bit, dual 16-bit banks,[7][15] 23.01136 MHz, 43ns)[6][7]

Notes

  1. ↑ [369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),[11] 32 cycles per divide 369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),[11] 32 cycles per divide]
  2. ↑ [390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),[11] 32 cycles per divide 390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),[11] 32 cycles per divide]
  3. ↑ [18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,[12][13][5] 2 framebuffer access cycles), 2 cycles per pixel[14] 18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,[12][13][5] 2 framebuffer access cycles), 2 cycles per pixel[14]]
  4. ↑ [724 cycles per polygon[15] 724 cycles per polygon[15]]
  5. ↑ [1492 cycles per polygon[15] 1492 cycles per polygon[15]]
  6. ↑ [5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon)
    • 258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access
    • 4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel)[17] 5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon)
    • 258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access
    • 4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel)[17]]

References

  1. ↑ Computer & Video Games, "May 1994" (UK; 1994-04-15), page 50
  2. ↑ GamePro, "April 1994" (US; 1994-xx-xx), page 160
  3. ↑ https://info.sonicretro.org/Sonic_the_Hedgehog_3/Development
  4. ↑ http://web.ncf.ca/au829/OutlawSprintCars/index.html
  5. ↑ 5.0 5.1 5.2 5.3 5.4 SVP Reference Guide (2008-02-06)
  6. ↑ 6.0 6.1 6.2 6.3 SVP documentation (2014-09-23)
  7. ↑ 7.0 7.1 7.2 7.3 7.4 7.5 7.6 File:SSP1601 datasheet.pdf
  8. ↑ 8.0 8.1 Sega's SVP Chip: The Road Not Taken
  9. ↑ 9.0 9.1 Virtua Racing (Euro)
  10. ↑ 10.0 10.1 File:TC511664B datasheet.pdf
  11. ↑ 11.0 11.1 Design of Digital Systems and Devices (pages 95-97)
  12. ↑ Algorithms for Parallel Polygon Rendering (pages 33-36)
  13. ↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
  14. ↑ Algorithms for Parallel Polygon Rendering (page 35)
  15. ↑ 15.0 15.1 15.2 SVP Register Guide (2008-02-06)
  16. ↑ Virtua Racing (IGN)
  17. ↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)
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