Sega NAOMI 2

Sega NAOMI 2

Manufacturer: Sega

Variants: Sega NAOMI 2 GD-ROM, Sega NAOMI 2 Satellite Terminal

Add-ons: GD-ROM

Release

Date

RRP

Code

World

2001^[1]

?

171‑8082C

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The Sega NAOMI 2 is an arcade board developed by Sega and is a successor to Sega NAOMI hardware. It was announced in 2000, with the first games utilising the technology shipping in 2001^[1].

Hardware

The NAOMI 2 is significantly more powerful than the NAOMI, including a dual CPU setup, new T&L GPU, dual rasterizer GPU, increased memory, and faster bandwidth. This leads to games with much more polygons than a NAOMI game, rendered at much faster speeds, while the new T&L GPU adds advanced lighting and particle effects. It was also more affordable than the very expensive (and difficult to program) Sega Hikaru arcade system that preceded it. The NAOMI 2 was nevertheless more powerful than home systems at the time.

As with the NAOMI, the NAOMI 2 was also available in GD-ROM and Satellite Terminal variants. By using similar architecture to the original NAOMI, it is fully backwards compatible with its predecessor.

Technical specifications

Main CPU: Hitachi SH‑4^[2] @ 200 MHz^[3]^[4]

Units: 128‑bit SIMD vector units with graphic functions, 2× 64‑bit floating‑point units, 2× 32‑bit fixed‑point units
Bus width: 128‑bit internal, 64‑bit external
Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
Fixed‑point performance: 360 MIPS
SH‑4 floating‑point performance: 1.4 GFLOPS
Note: With Elan used as geometry coprocessor, the SH‑4's 128‑bit SIMD matrix unit can be dedicated to game physics, artificial intelligence, collision detection, overall game code, or further enhancing graphics. CPU load is reduced by 90% with Elan.^[5]

Sound engine: Yamaha AICA Super Intelligent Sound Processor @ 67 MHz

Internal CPU: 32‑bit ARM7 RISC CPU @ 45 MHz
CPU performance: 17 MIPS
PCM/ADPCM: 16‑bit depth, 48 kHz sampling rate (DVD quality), 64 channels
Other features: DSP, sound synthesizer

PLD: 4 PLD^{[n 1]}

Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz^{[n 2]}
Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6 MHz^{[n 3]}
Sega 315‑6268 (Altera EPM7032AELC44‑10) CPLD @ 103.1 MHz^{[n 4]}
Sega 315‑6269 (Altera MAX EPM7064AETC100‑10) CPLD @ 100 MHz^{[n 5]}

Operating systems:

Sega native operating system
Custom Windows CE, with DirectX 6.0, Direct3D and OpenGL support

Storage media: ROM cartridge
Extensions: communication, 4‑channel surround sound, PCI, MIDI, RS‑232C
Connection: JAMMA Video compliant

Graphics

GPU: 6 core processors (Elan, SH‑4 SIMD, 2× PowerVR2, 2 DAC)

Core units: 14 units (Elan, SH‑4 SIMD, 10 PowerVR2 cores, 2 DAC)
Clock rate: 200 MHz

GPU T&L geometry coprocessor: VideoLogic Elan @ 100 MHz

Bus width: 512‑bit (4× 128‑bit)^[9]
Lighting: Up to 16 light sources per polygon, ambient lighting, parallel lighting, point lighting, spotlight lighting
Vertex support: Combined dynamic and static model processing
Features: Reduces CPU load to 1/10th (90% reduction), multiple light type support (ambient, parallel, point, spot), hardware Z clipping, offscreen & backface culling^[5]
Elan floating‑point performance: 7.5 GFLOPS^[10]^{[n 6]}

GPU rasterizers: 2× NEC‑VideoLogic PowerVR2 @ 100 MHz

Revision: Dual PowerVR2 doubles rendering performance over NAOMI, which in turn had twice the rendering performance of the Dreamcast, as NAOMI revision has dual ISP cores in each PowerVR2^{[n 7]}
Bus width: 128‑bit (external)
Cores: 2x TA (Tile Accelerators), 4x ISP (Image Synthesis Processors), 2x TSP (Texture & Shading Processor), 6x Triangle Setup FPU, 2x RAMDAC

Units: 176 rendering units (148 ISP units, 20 TSP units, 6 FPU units, 2 RAMDAC)

ISP units: 4x ISP Precalc Units, 4x ISP PE Arrays (128 PE processor elements), 4x Depth Accumulation Buffers, 4x Span RLC, 4x Span Sorters, 4x ISP Parameter Cache
TSP units: 2x TSP Precalc, 2x Parameter Cache, 2x Texture Cache, 2x Iterator Arrays, 2x Pixel Processing Engines, 2x Tile Accumulation Buffers, 2x Secondary Accumulation Buffers, 2x Combine & Bump Map Units, 2x Fog Units, 2x Alpha Blending Units^[15]
Triangle Setup FPU: 6 FPU rendering units, 2.1 GFLOPS

4x ISP Setup FPU: 100 MHz, 1457 MFLOPS, surface and culling processing for polygons, 28,571,428 polygons/sec^{[n 8]}
2x TSP Setup FPU: 100 MHz, 728 MFLOPS, shading and texture processing^[16] for tiles processed by ISP^[12]

RAMDAC: 230 MHz
Effects: Bump mapping, multi‑texturing, fog, alpha blending, mipmapping, bilinear filtering, trilinear filtering, anti‑aliasing, environment mapping, specular effects,^[18]^[19] normal mapping
Features: Tiled rendering, deferred rendering, back‑face culling, hidden surface removal
Defails: See NAOMI Specifications and Dreamcast Specifications for more details on PowerVR2 graphics system.

Video DAC: 2× Rohm BU1426KS @ 35.4695 MHz^[20]

Bus width: 48‑bit (2× 24‑bit)

Color depth: 32‑bit ARGB, 16,777,216 colors (24‑bit color) with 8‑bit (256 levels) alpha blending, YUV and RGB color spaces, color key overlay^[21]
Display resolution: 31 kHz horizontal sync, 60 Hz refresh rate, JAMMA/VGA,^[22] progressive scan

Single monitor: 496×384 to 800×608 pixels^[23]
Dual monitor: 992×768 to 1600×608 pixels

Rendering fillrate:

12 GPixels/s: Maximum fillrate for opaque polygons^{[n 9]}
2 GPixel/s: Average fillrate for translucent and opaque polygons^[3]^{[n 10]}
400 MPixels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60^{[n 11]}

Texture fillrate:^{[n 12]}

12 GTexels/s: Maximum fillrate for opaque polygons
2 GTexel/s: Average fillrate for translucent and opaque polygons
400 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60

Textures per pass: 10 texture layers^[10]
Floating-point performance: 11 GFLOPS

Elan: 7.5 GFLOPS geometry
SH-4 SIMD: 1.4 GFLOPS geometry
PowerVR2: 2.1 GFLOPS rendering

T&L geometry: 8.7 GFLOPS^{[n 13]}

Matrix transformations: 240 million vertices/sec^{[n 14]}
Perspective transformations: 210 million vertices/sec^{[n 15]}
1 light source: 110 million vertices/sec^{[n 16]}
4 light sources: 26 million vertices/sec^{[n 17]}
6 light sources: 18 million vertices/sec^{[n 18]}

Polygon rendering performance: Gouraud shading

100 million polygons/sec: 1 light source^[10]
26 million polygons/sec: 4 light sources, texture mapping
10 million polygons/sec: 6 light sources, texture mapping

Memory

Overall memory: 304–584 MB (136 MB RAM, 168–448 MB ROM)

Video memory: 240–352 MB (96 MB RAM, 144–256 MB ROM)

Internal processor cache: 422 KB^{[n 19]}^[31]

SH4 CPU cache: 281.564 KB^{[n 20]}
PowerVR2 GPU cache: 92 KB^{[n 21]}
AICA audio cache: 32.011 KB^{[n 22]}
I/O Board MCU: 16.5 KB^{[n 23]}

System RAM: 136 MB^[2]

Main RAM: 32 MB SDRAM
VRAM: 96 MB

Elan: 32 MB SDRAM (geometry/model data)
PowerVR2: 64 MB SDRAM^{[n 24]}

Sound RAM: 8 MB
FPGA Configuration: 8 KB SRAM^[2]^[7]
Backup SRAM: 32 KB^[33]

System ROM: 2048.25 KB^{[n 25]}
Cartridge ROM: 168–448 MB

2000 format: 168–280 MB^{[n 26]}
2005 format: Up to 448 MB^{[n 27]}

Bandwidth

Internal processor cache bandwidth:

SH4 cache: 3.2 GB/s^{[n 28]}
GPU cache:

Elan: 6.4 GB/s^{[n 29]}
PowerVR2: 57 GB/s^{[n 30]}
DAC: 213 MB/s^{[n 31]}

AICA: 256 MB/s^{[n 32]}
PLD: 9.3 GB/s^{[n 33]}

RAM/ROM memory bandwidth: 16.1 GB/s (15.1 GB/s system, 1 GB/s cartridge)

Video memory: 14.01 GB/s (13.01 GB/s VRAM, 900 MB/s ROM)

System RAM bandwidth: 10 GB/s^[2]

Main RAM: 1.6 GB/s^{[n 34]}
VRAM: 8.4 GB/s

Elan: 6.4 GB/s^{[n 35]}
PowerVR2: 2 GB/s^{[n 36]}

Sound RAM: 132 MB/s^{[n 37]}
Backup SRAM: 44 MB/s^{[n 38]}
FPGA Configuration: 6 MB/s^{[n 39]}

System ROM bandwidth: 88 MB/s^[2]

BIOS EPROM: 80 MB/s^{[n 40]}
EEPROM: 8 MB/s^{[n 41]}

Cartridge ROM bandwidth: 900 MB/s^{[n 42]}

Note: High‑speed access allows ROM to effectively be used as RAM, and textures streamed directly from ROM.^[45]

Cartridge RAM bandwidth: 100 MB/s^{[n 43]}

NAOMI 2 GD-ROM Specifications

The NAOMI GD‑ROM, released in 2001, is identical to the standard NAOMI, but uses GD‑ROM discs for storage instead of ROM cartridges. It comes with a DIMM Board, which is very similar to a ROM cartridge, but with RAM instead of ROM. When a game is installed, the GD‑ROM content is loaded onto the DIMM Board RAM, so that the game data runs from the DIMM Board rather than the GD‑ROM disc. The NAOMI 2 GD‑ROM specification includes the following differences:

Board composition: Motherboard + Daughter Board + DIMM Board
Storage media: GD‑ROM drive

GD‑ROM transfer rate: 1.8 MB/s (1800 KB/sec)

Memory

RAM: 392–648 MB (SDRAM)

Main RAM: 32 MB
VRAM: 96 MB
Sound RAM: 8 MB
DIMM RAM: 256–512 MB^[46]

L2 cache: 256 KB
ROM: 26 MB

System ROM: 2048.25 KB^{[n 44]}
DIMM ROM: 24 MB (EPROM)

Bandwidth

RAM bandwidth: 11–12 GB/s

Main RAM: 1.6 GB/s
VRAM: 8.4 GB/s
Sound RAM: 132 MB/s
SRAM: 44 MB/s
DIMM RAM: 1.1–2.13 GB/s^{[n 45]}

List of games

NAOMI 2

Jet Squadron (prototype) (2000)

NAOMI 2 GD-ROM

Virtua Striker 3 (2001)
Virtua Fighter 4 (2001)
Beach Spikers: Virtua Beach Volleyball (2001)
Initial D: Arcade Stage (2002)
Initial D: Arcade Stage Ver. 2 (2002)
Virtua Fighter 4 Final Tuned (2004)
Initial D Arcade Stage Ver. 3 (2004)

NAOMI 2 Satellite Terminal

World Club Champion Football: Serie A 2001-2002 (2002)
World Club Champion Football: Serie A 2002-2003 (2003)
World Club Champion Football: European Clubs 2004-2005 (2005)
World Club Champion Football: European Clubs 2005-2006 (2006)

History

VideoLogic's Elan, the T&L geometry GPU coprocessor used in the NAOMI 2, had been in development since 1998, when the original NAOMI arcade system and Dreamcast console launched.^[48] Yu Suzuki was involved in its development, insisting that it must have enough power to sustain in-game performance of at least 10 million polygons per second with all effects enabled.^[49] It was also more affordable than the very expensive (and difficult to program) Sega Hikaru arcade system that preceded it.^[50] The NAOMI 2 was nevertheless more powerful than home systems at the time.

Production credits

Hiroshi Yagi

Source:

Developer mentions^[51]

Digital Manuals

EN Manual - Sega Corp (420-6644-01)

Notes

↑ [49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[2] 49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[2]]
↑ [42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[6] 5.3 GB/s 42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[6] 5.3 GB/s]
↑ [8‑bit,^[7] 6 MB/s 8‑bit,^[7] 6 MB/s]
↑ [2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[8] 1.3403 GB/s 2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[8] 1.3403 GB/s]
↑ [4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[8] 2.6 GB/s 4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[8] 2.6 GB/s]
↑ [75 floating-point operations per cycle 75 floating-point operations per cycle]
↑ [Scaled for high-end arcade technology,^[11] with parallel ISP cores and increased PE processing elements within processor.^[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,^[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[14] Scaled for high-end arcade technology,^[11] with parallel ISP cores and increased PE processing elements within processor.^[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,^[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[14]]
↑ [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles^[16]^[17] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles^[16]^[17]]
↑ [32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP) 32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP)]
↑ [20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP) 20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP)]
↑ [60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP) 60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP)]
↑ [Same as pixel rendering fillrate Same as pixel rendering fillrate]
↑ [Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS) Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS)]
↑ [Elan: 200 million vertices/sec (28 floating-point operations per transform,^[24] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[25] Elan: 200 million vertices/sec (28 floating-point operations per transform,^[24] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[25]]
↑ [Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,^[24] 3 operations for perspective division),^[26] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[25] 5 cycles perspective division),^[26] 12 cycles division latency^[27] Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,^[24] 3 operations for perspective division),^[26] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[25] 5 cycles perspective division),^[26] 12 cycles division latency^[27]]
↑ [Elan: 100 million vertices/sec (63 floating-point operations per vertex,^[28] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[29]^[30] Elan: 100 million vertices/sec (63 floating-point operations per vertex,^[28] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[29]^[30]]
↑ [Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
↑ [Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
↑ [432,206 bytes 432,206 bytes]
↑ [288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[10] 288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[10]]
↑ [94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer 94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer]
↑ [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]
↑ [16,896 bytes: 512 bytes RAM, 16 KB ROM^[32] 16,896 bytes: 512 bytes RAM, 16 KB ROM^[32]]
↑ [2× 32 MB 2× 32 MB]
↑ [2 MB BIOS EPROM, 256 bytes EEPROM^[2] 2 MB BIOS EPROM, 256 bytes EEPROM^[2]]
↑ [24 MB EPROM,^[34] 144–256 MB FlashROM/MROM 24 MB EPROM,^[34] 144–256 MB FlashROM/MROM]
↑ [128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[35] 128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[35]]
↑ [128‑bit, 200 MHz 128‑bit, 200 MHz]
↑ [512‑bit, 100 MHz 512‑bit, 100 MHz]
↑ [2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,^[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,^[37] 4x 1024-bit ISP PE Arrays,^[12] 2x 64-bit TSP Texture Cache,^[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer 2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,^[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,^[37] 4x 1024-bit ISP PE Arrays,^[12] 2x 64-bit TSP Texture Cache,^[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer] (archive.today)
↑ [48‑bit, 35.4695 MHz 48‑bit, 35.4695 MHz]
↑ [32‑bit, 67 MHz 32‑bit, 67 MHz]
↑ [656‑bit, 125 MHz 656‑bit, 125 MHz]
↑ [128‑bit, 100 MHz^[39] 128‑bit, 100 MHz^[39]]
↑ [512‑bit, 100 MHz^[9] 512‑bit, 100 MHz^[9]]
↑ [128‑bit, 125 MHz^[40] 128‑bit, 125 MHz^[40]]
↑ [16‑bit, 66 MHz 16‑bit, 66 MHz]
↑ [16‑bit, 22 MHz^[33] 16‑bit, 22 MHz^[33]]
↑ [8‑bit, 6 MHz^[7] 8‑bit, 6 MHz^[7]]
↑ [16‑bit, 40 MHz^[41]^[42] 16‑bit, 40 MHz^[41]^[42]]
↑ [2× 16‑bit, 2 MHz^[43] 2× 16‑bit, 2 MHz^[43]]
↑ [50 MHz^[44] 50 MHz^[44]]
↑ [16‑bit, 50 MHz 16‑bit, 50 MHz]
↑ [24 MB BIOS EPROM, 256 bytes EEPROM 24 MB BIOS EPROM, 256 bytes EEPROM]
↑ [1/2× 64‑bit, 133 MHz^[46]^[47] 1/2× 64‑bit, 133 MHz^[46]^[47]]

References

↑ ^1.0 ^1.1 http://www.sega.co.jp/sega/corp/news/nr000921_3.html (Wayback Machine: 2000-12-03 04:43)
↑ ^2.0 ^2.1 ^2.2 ^2.3 ^2.4 ^2.5 ^2.6 Sega NAOMI / NAOMI 2 (MAME)
↑ ^3.0 ^3.1 DC-UK, "December 2000" (UK; 2000-10-23), page 41
↑ File:SH-4 Software Manual.pdf
↑ ^5.0 ^5.1 Press release: 2000-09-21: Sega Announces NAOMI2 Next Generation Arcade Systems Using Imagination Technologies’ PowerVR Graphics Architecture
↑ File:EPF8452A datasheet.pdf
↑ ^7.0 ^7.1 ^7.2 File:EPC1064 datasheet.pdf
↑ ^8.0 ^8.1 File:EPM7032AE datasheet.pdf
↑ ^9.0 ^9.1 File:UPD4564323 datasheet.pdf
↑ ^10.0 ^10.1 ^10.2 ^10.3 NAOMI 2 Specifications (May 31, 2001)
↑ File:PowerVR.pdf, page 2
↑ ^12.0 ^12.1 ^12.2 File:PowerVR.pdf, page 3
↑ Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM
↑ Edge, "January 1999" (UK; 1998-12-23), page 11
↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 110
↑ ^16.0 ^16.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 95
↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 203
↑ JAMMA 2000: NAOMI 2 Revealed (September 20, 2000)
↑ File:NAOMI 1998 Press Release JP.pdf
↑ File:BU142 datasheet.pdf
↑ http://www3.sharkyextreme.com/hardware/reviews/video/neon250/2.shtml (Wayback Machine: 2007-08-11 10:20)
↑ Sega Naomi Universal
↑ Dreamcast Video (KallistiOS)
↑ ^24.0 ^24.1 Design of Digital Systems and Devices (page 95)
↑ ^25.0 ^25.1 File:SH-4 Next-Generation DSP Architecture.pdf, page 12
↑ ^26.0 ^26.1 Dreamcast: Basic matrix operations (KallistiOS)
↑ File:SH-4 Software Manual.pdf, page 211
↑ Design of Digital Systems and Devices (page 96)
↑ File:SH-4 Software Manual.pdf, page 151
↑ File:SH-4 Next-Generation DSP Architecture.pdf, page 31
↑ File:DreamcastDevBoxSystemArchitecture.pdf
↑ File:TMP90PH44 datasheet.pdf
↑ ^33.0 ^33.1 File:HM62256B datasheet.pdf
↑ Club Kart: European Session (MAME)
↑ File:XCF01S datasheet.pdf
↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 165
↑ http://mc.pp.se/dc/pvr.html (archive.today)
↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 96
↑ File:HM5264 datasheet.pdf
↑ File:HY57V161610D datasheet.pdf
↑ File:CY2292 datasheet.pdf
↑ File:M27C160 datasheet.pdf
↑ File:AT93C46 datasheet.pdf
↑ File:S29GL-N datasheet.pdf
↑ Hideki Sato Sega Inteview (Edge)
↑ ^46.0 ^46.1 Sega Naomi DIMM board and GD-ROM
↑ File:M366S3323CT0 datasheet.pdf
↑ http://www.techweb.com/wire/story/TWB19980923S0008 (Wayback Machine: 1998-12-06 11:10)
↑ Next Generation, "May 2001" (US; 2001-04-17), page 61
↑ Next Generation, "April 2001" (US; 2001-03-20), page 37
↑ https://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)

Sega arcade boards
Originating in arcades
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 VIC Dual G80 Zaxxon VCO Object System 1 LaserDisc Appoooh Hang-On System 2 System 16 OutRun Gigas X Board Y Board System 24 System 18 System 32 Model 1 Model 2 H1 Board Model 3
Console-based hardware
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SG-1000 System E System C Mega-Tech System Mega Play Sega Titan Video NAOMI Hikaru NAOMI 2 Atomiswave System SP Chihiro Triforce
PC-based hardware
05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Lindbergh Europa-R RingEdge RingWide RingEdge 2 Nu Nu 1.1 Nu 2 ALLS

[49.26nbsp.3Bunits.2C_656.E2.80.91bit_internal.2C_224.E2.80.91bit_external.2C_125.26nbsp.3BMHz.2C_9.25.26nbsp.3BGB.2Fs.7F.27.22.60UNIQ--ref-0000000D-QINU.60.22.27.7F-6] [49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[2] 49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s^[2]]

[42.26nbsp.3Bunits.2C_336.E2.80.91bit_.2842.C3.97.26nbsp.3B8.E2.80.91bit.29_internal.2C_120.E2.80.91bit_external.2C.7F.27.22.60UNIQ--ref-00000011-QINU.60.22.27.7F_5.3.26nbsp.3BGB.2Fs-8] [42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[6] 5.3 GB/s 42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,^[6] 5.3 GB/s]

[8.E2.80.91bit.2C.7F.27.22.60UNIQ--ref-00000015-QINU.60.22.27.7F_6.26nbsp.3BMB.2Fs-10] [8‑bit,^[7] 6 MB/s 8‑bit,^[7] 6 MB/s]

[2.26nbsp.3Bunits.2C_104.E2.80.91bit_.282.C3.97.26nbsp.3B52.E2.80.91bit.29_internal.2C_32.E2.80.91bit_.282.C3.97.26nbsp.3B16.E2.80.91bit.29_external.2C.7F.27.22.60UNIQ--ref-00000019-QINU.60.22.27.7F_1.3403.26nbsp.3BGB.2Fs-12] [2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[8] 1.3403 GB/s 2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,^[8] 1.3403 GB/s]

[4.26nbsp.3Bunits.2C_208.E2.80.91bit_.284.C3.97.26nbsp.3B52.E2.80.91bit.29_internal.2C_64.E2.80.91bit_.284.C3.97.26nbsp.3B16.E2.80.91bit.29_external.2C.7F.27.22.60UNIQ--ref-0000001D-QINU.60.22.27.7F_2.6.26nbsp.3BGB.2Fs-13] [4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[8] 2.6 GB/s 4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,^[8] 2.6 GB/s]

[75_floating-point_operations_per_cycle-16] [75 floating-point operations per cycle 75 floating-point operations per cycle]

[Scaled_for_high-end_arcade_technology.2C.7F.27.22.60UNIQ--ref-00000027-QINU.60.22.27.7F_with_parallel_ISP_cores_and_increased_PE_processing_elements_within_processor..7F.27.22.60UNIQ--ref-0000002A-QINU.60.22.27.7F_NAOMI_2_has_average_fillrate_of_2_gigapixels.2Fsec.2C_twice_that_of_the_NAOMI.27s_average_1_gigapixel.2Fsec_fillrate.2C.7F.27.22.60UNIQ--ref-0000002B-QINU.60.22.27.7F_which_in_turn_is_twice_that_of_the_Dreamcast.27s_average_500_megapixels.2Fsec_fillrate..7F.27.22.60UNIQ--ref-0000002E-QINU.60.22.27.7F-21] [Scaled for high-end arcade technology,^[11] with parallel ISP cores and increased PE processing elements within processor.^[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,^[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[14] Scaled for high-end arcade technology,^[11] with parallel ISP cores and increased PE processing elements within processor.^[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,^[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[14]]

[14_cycles.2Fpolygon_per_ISP_FPU.2C_51_floating-point_operations_per_polygon.2C_204_floating-point_operations_per_14_cycles.7F.27.22.60UNIQ--ref-00000035-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000038-QINU.60.22.27.7F-25] [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles^[16]^[17] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles^[16]^[17]]

[32_pixels.2Fcycle_per_ISP.2C1_pixel_per_PE_.28processor_element.29.2C_128_PE_.2832_PE_per_ISP.2C_64_PE_per_PowerVR2.29.2C_6_gigapixels.2Fsec_per_PowerVR2_.283.2_gigapixels.2Fsec_per_ISP.29-32] [32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP) 32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP)]

[20_pixels_per_cycle.2C_6_PEs_.28processor_elements.29_per_pixel.2C_1_gigapixel_per_PowerVR2_.28500_megapixels.2Fsec_per_ISP.29-33] [20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP) 20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP)]

[60_layers_depth.2C_4_pixels_per_cycle_.282_pixels_per_PowerVR2.29.2C_32_PEs_per_pixel.2C_200_megapixels.2Fsec_per_PowerVR2_.28100_megapixels.2Fsec_per_ISP.29-34] [60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP) 60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP)]

[Same_as_pixel_rendering_fillrate-35] [Same as pixel rendering fillrate Same as pixel rendering fillrate]

[Elan:_7.5_GFLOPS_.2875_floating-point_operations_per_cycle.29_.3Cbr.3E_SH.E2.80.914_SIMD:_180_MHz_available_.2810.25_load.2C_20_MHz_used.29.2C_1.26_GFLOPS_.2890.25_of_1.4_GFLOPS.29-36] [Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS) Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS)]

[Elan:_200_million_vertices.2Fsec_.2828_floating-point_operations_per_transform.2C.7F.27.22.60UNIQ--ref-00000053-QINU.60.22.27.7F_2_transforms_per_cycle.29_.3Cbr.3E_SH-4:_45_million_vertices.2Fsec_.284_cycles_per_transform.29.7F.27.22.60UNIQ--ref-00000056-QINU.60.22.27.7F-39] [Elan: 200 million vertices/sec (28 floating-point operations per transform,^[24] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[25] Elan: 200 million vertices/sec (28 floating-point operations per transform,^[24] 2 transforms per cycle)
SH-4: 45 million vertices/sec (4 cycles per transform)^[25]]

[Elan:_200_million_vertices.2Fsec.2C_31_floating-point_operations_per_vertex_.2828_operations_for_matrix_transform.2C.7F.27.22.60UNIQ--ref-00000058-QINU.60.22.27.7F_3_operations_for_perspective_division.29.2C.7F.27.22.60UNIQ--ref-00000059-QINU.60.22.27.7F_2_transforms_per_cycle_.3Cbr.3E_SH-4:_15_million_vertices.2Fsec.2C_12_cycles_per_vertex_.284_cycles_matrix_transform.2C.7F.27.22.60UNIQ--ref-0000005C-QINU.60.22.27.7F_5_cycles_perspective_division.29.2C.7F.27.22.60UNIQ--ref-0000005D-QINU.60.22.27.7F_12_cycles_division_latency.7F.27.22.60UNIQ--ref-00000060-QINU.60.22.27.7F-42] [Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,^[24] 3 operations for perspective division),^[26] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[25] 5 cycles perspective division),^[26] 12 cycles division latency^[27] Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,^[24] 3 operations for perspective division),^[26] 2 transforms per cycle
SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,^[25] 5 cycles perspective division),^[26] 12 cycles division latency^[27]]

[Elan:_100_million_vertices.2Fsec_.2863_floating-point_operations_per_vertex.2C.7F.27.22.60UNIQ--ref-00000062-QINU.60.22.27.7F_1_vertex_per_cycle.29_.3Cbr.3E_SH-4:_12_million_vertices.2Fsec.2C_14_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_surface_normal.2C_4_cycles_lighting_matrix.29.7F.27.22.60UNIQ--ref-00000065-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000068-QINU.60.22.27.7F-46] [Elan: 100 million vertices/sec (63 floating-point operations per vertex,^[28] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[29]^[30] Elan: 100 million vertices/sec (63 floating-point operations per vertex,^[28] 1 vertex per cycle)
SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)^[29]^[30]]

[Elan:_20_million_vertices.2Fsec.2C_5_cycles_per_vertex_.281_cycle_transform.2C_1_cycle_per_light_source.29_.3Cbr.3E_SH-4:_6_million_vertices.2Fsec.2C_29_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_per_surface_normal.2C_4_cycles_per_lighting_matrix.29-47] [Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]

[Elan:_14_million_vertices.2Fsec.2C_7_cycles_per_vertex_.281_cycle_transform.2C_1_cycle_per_light_source.29_.3Cbr.3E_SH-4:_4_million_vertices.2Fsec.2C_39_cycles_per_vertex_.284_cycles_matrix_transformation.2C_5_cycles_perspective_division.2C_1_cycle_per_surface_normal.2C_4_cycles_per_lighting_matrix.29-48] [Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]

[432.2C206_.5B.5Bbyte.5D.5Ds-49] [432,206 bytes 432,206 bytes]

[288.2C322_bytes:_8_KB_instruction_cache.2C_16_KB_data_cache.2C_64_bytes_store_queue_cache.2C_1538_bytes_registers.2C_256.26nbsp.3BKB_.5B.5Bwikipedia:L2_cache.7CL2_cache.5D.5D.7F.27.22.60UNIQ--ref-00000071-QINU.60.22.27.7F-51] [288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[10] 288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache^[10]]

[94.2C208_bytes:_16.5_KB_register_memory.2C_49_KB_ISP_cache.2C_26_KB_TSP_cache.2C_512_bytes_FIFO_buffer-52] [94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer 94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer]

[32.2C780_bytes:_32_KB_sound_registers.2C_8_bytes_RTC_registers.2C_4_bytes_FIFO_buffer-53] [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]

[16.2C896_bytes:_512.26nbsp.3Bbytes_RAM.2C_16.26nbsp.3BKB_ROM.7F.27.22.60UNIQ--ref-00000077-QINU.60.22.27.7F-55] [16,896 bytes: 512 bytes RAM, 16 KB ROM^[32] 16,896 bytes: 512 bytes RAM, 16 KB ROM^[32]]

[2.C3.97.26nbsp.3B32.26nbsp.3BMB-56] [2× 32 MB 2× 32 MB]

[2.26nbsp.3BMB_.5B.5BBIOS.5D.5D_.5B.5BEPROM.5D.5D.2C_256.26nbsp.3Bbytes_.5B.5BEPROM.7CEEPROM.5D.5D.7F.27.22.60UNIQ--ref-00000082-QINU.60.22.27.7F-58] [2 MB BIOS EPROM, 256 bytes EEPROM^[2] 2 MB BIOS EPROM, 256 bytes EEPROM^[2]]

[24.26nbsp.3BMB_.5B.5BEPROM.5D.5D.2C.7F.27.22.60UNIQ--ref-00000084-QINU.60.22.27.7F_144.E2.80.93256_MB_.5B.5Bwikipedia:FlashROM.7CFlashROM.5D.5D.2F.5B.5Bwikipedia:Mask_ROM.7CMROM.5D.5D-60] [24 MB EPROM,^[34] 144–256 MB FlashROM/MROM 24 MB EPROM,^[34] 144–256 MB FlashROM/MROM]

[128.E2.80.93448.26nbsp.3BMB_FlashROM.2C_0.E2.80.9340.26nbsp.3BMB_EPROM.2C_128.26nbsp.3BKB_Flash_.5B.5Bwikipedia:Programmable_read-only_memory.7CPROM.5D.5D.7F.27.22.60UNIQ--ref-00000088-QINU.60.22.27.7F-62] [128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[35] 128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM^[35]]

[128.E2.80.91bit.2C_200.26nbsp.3BMHz-63] [128‑bit, 200 MHz 128‑bit, 200 MHz]

[512.E2.80.91bit.2C_100.26nbsp.3BMHz-64] [512‑bit, 100 MHz 512‑bit, 100 MHz]

[2x_2304.E2.80.91bit.2C_100_MHz:_2x_32-bit_TA_tile_buffer.2C.7F.27.22.60UNIQ--ref-0000008E-QINU.60.22.27.7F_4x_32-bit_ISP_registers.2C_2x_32-bit_TSP_registers.2C.7F.27.22.60UNIQ--ref-0000008F-QINU.60.22.27.7F_4x_1024-bit_ISP_PE_Arrays.2C.7F.27.22.60UNIQ--ref-00000092-QINU.60.22.27.7F_2x_64-bit_TSP_Texture_Cache.2C.7F.27.22.60UNIQ--ref-00000095-QINU.60.22.27.7F_2x_32-bit_TSP_Tile_Accumulation_Buffer.2C_2x_32-bit_Secondary_Accumulation_Buffer-68] [2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,^[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,^[37] 4x 1024-bit ISP PE Arrays,^[12] 2x 64-bit TSP Texture Cache,^[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer 2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,^[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,^[37] 4x 1024-bit ISP PE Arrays,^[12] 2x 64-bit TSP Texture Cache,^[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer] (archive.today)

[48.E2.80.91bit.2C_35.4695.26nbsp.3BMHz-69] [48‑bit, 35.4695 MHz 48‑bit, 35.4695 MHz]

[32.E2.80.91bit.2C_67.26nbsp.3BMHz-70] [32‑bit, 67 MHz 32‑bit, 67 MHz]

[656.E2.80.91bit.2C_125.26nbsp.3BMHz-71] [656‑bit, 125 MHz 656‑bit, 125 MHz]

[128.E2.80.91bit.2C_100.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-0000009D-QINU.60.22.27.7F-73] [128‑bit, 100 MHz^[39] 128‑bit, 100 MHz^[39]]

[512.E2.80.91bit.2C_100.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000A1-QINU.60.22.27.7F-74] [512‑bit, 100 MHz^[9] 512‑bit, 100 MHz^[9]]

[128.E2.80.91bit.2C_125.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000A5-QINU.60.22.27.7F-76] [128‑bit, 125 MHz^[40] 128‑bit, 125 MHz^[40]]

[16.E2.80.91bit.2C_66.26nbsp.3BMHz-77] [16‑bit, 66 MHz 16‑bit, 66 MHz]

[16.E2.80.91bit.2C_22.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000AA-QINU.60.22.27.7F-78] [16‑bit, 22 MHz^[33] 16‑bit, 22 MHz^[33]]

[8.E2.80.91bit.2C_6.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000AE-QINU.60.22.27.7F-79] [8‑bit, 6 MHz^[7] 8‑bit, 6 MHz^[7]]

[16.E2.80.91bit.2C_40.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000B3-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000B6-QINU.60.22.27.7F-82] [16‑bit, 40 MHz^[41]^[42] 16‑bit, 40 MHz^[41]^[42]]

[2.C3.97.26nbsp.3B16.E2.80.91bit.2C_2.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000BA-QINU.60.22.27.7F-84] [2× 16‑bit, 2 MHz^[43] 2× 16‑bit, 2 MHz^[43]]

[50.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000BE-QINU.60.22.27.7F-86] [50 MHz^[44] 50 MHz^[44]]

[16.E2.80.91bit.2C_50.26nbsp.3BMHz-88] [16‑bit, 50 MHz 16‑bit, 50 MHz]

[24.26nbsp.3BMB_BIOS_EPROM.2C_256.26nbsp.3Bbytes_EEPROM-90] [24 MB BIOS EPROM, 256 bytes EEPROM 24 MB BIOS EPROM, 256 bytes EEPROM]

[1.2F2.C3.97.26nbsp.3B64.E2.80.91bit.2C_133.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000C4-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000C7-QINU.60.22.27.7F-92] [1/2× 64‑bit, 133 MHz^[46]^[47] 1/2× 64‑bit, 133 MHz^[46]^[47]]

[https:.2F.2Fweb.archive.org.2Fweb.2F20001203044300.2Fhttp:.2F.2Fwww.sega.co.jp.2Fsega.2Fcorp.2Fnews.2Fnr000921_3.html-1] 1.0 ^1.1 http://www.sega.co.jp/sega/corp/news/nr000921_3.html (Wayback Machine: 2000-12-03 04:43)

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fnaomi.cpp_Sega_NAOMI_.2F_NAOMI_2_.28MAME.29.5D-2] 2.0 ^2.1 ^2.2 ^2.3 ^2.4 ^2.5 ^2.6 Sega NAOMI / NAOMI 2 (MAME)

[:File:DCUK_16.pdf_p41-3] 3.0 ^3.1 DC-UK, "December 2000" (UK; 2000-10-23), page 41

[:File:SH-4_Software_Manual.pdf_p-4] File:SH-4 Software Manual.pdf

[Press_release:_2000-09-21:_Sega_Announces_NAOMI2_Next_Generation_Arcade_Systems_Using_Imagination_Technologies.E2.80.99_PowerVR_Graphics_Architecture-5] 5.0 ^5.1 Press release: 2000-09-21: Sega Announces NAOMI2 Next Generation Arcade Systems Using Imagination Technologies’ PowerVR Graphics Architecture

[:File:EPF8452A_datasheet.pdf_p-7] File:EPF8452A datasheet.pdf

[:File:EPC1064_datasheet.pdf_p-9] 7.0 ^7.1 ^7.2 File:EPC1064 datasheet.pdf

[:File:EPM7032AE_datasheet.pdf_p-11] 8.0 ^8.1 File:EPM7032AE datasheet.pdf

[:File:UPD4564323_datasheet.pdf_p-14] 9.0 ^9.1 File:UPD4564323 datasheet.pdf

[.5Bhttp:.2F.2Fwww.ign.com.2Fboards.2Fthreads.2Fnoami-2-future.6157195.2F_NAOMI_2_Specifications_.28May_31.2C_2001.29.5D-15] 10.0 ^10.1 ^10.2 ^10.3 NAOMI 2 Specifications (May 31, 2001)

[:File:PowerVR.pdf_p2-17] File:PowerVR.pdf, page 2

[:File:PowerVR.pdf_p3-18] 12.0 ^12.1 ^12.2 File:PowerVR.pdf, page 3

[Press_release:_1998-09-17:_SEGA_SELECTS_POWERVR_SERIES2_AS_3D_GRAPHICS_TECHNOLOGY_FOR_NEW_ARCADE_SYSTEM-19] Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM

[:File:Edge_UK_067.pdf_p11-20] Edge, "January 1999" (UK; 1998-12-23), page 11

[:File:DreamcastDevBoxSystemArchitecture.pdf_p110-22] File:DreamcastDevBoxSystemArchitecture.pdf, page 110

[:File:DreamcastDevBoxSystemArchitecture.pdf_p95-23] 16.0 ^16.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 95

[:File:DreamcastDevBoxSystemArchitecture.pdf_p203-24] File:DreamcastDevBoxSystemArchitecture.pdf, page 203

[.5Bhttp:.2F.2Fign.com.2Farticles.2F2000.2F09.2F21.2Fjamma-2000-naomi-2-revealed_JAMMA_2000:_NAOMI_2_Revealed_.28September_20.2C_2000.29.5D-26] JAMMA 2000: NAOMI 2 Revealed (September 20, 2000)

[:File:NAOMI_1998_Press_Release_JP.pdf_p-27] File:NAOMI 1998 Press Release JP.pdf

[:File:BU142_datasheet.pdf_p-28] File:BU142 datasheet.pdf

[http:.2F.2Fweb.archive.org.2Fweb.2F20070811102018.2Fhttp:.2F.2Fwww3.sharkyextreme.com.2Fhardware.2Freviews.2Fvideo.2Fneon250.2F2.shtml-29] ttp://www3.sharkyextreme.com/hardware/reviews/video/neon250/2.shtml (Wayback Machine: 2007-08-11 10:20)

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_Universal_Sega_Naomi_Universal.5D-30] Sega Naomi Universal

[.5Bhttp:.2F.2Fcadcdev.sourceforge.net.2Fdocs.2Fkos-current.2Fvideo_8h_source.html_Dreamcast_Video_.28KallistiOS.29.5D-31] Dreamcast Video (KallistiOS)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA95_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28page_95.29.5D-37] 24.0 ^24.1 Design of Digital Systems and Devices (page 95)

[:File:SH-4_Next-Generation_DSP_Architecture.pdf_p12-38] 25.0 ^25.1 File:SH-4 Next-Generation DSP Architecture.pdf, page 12

[.5Bhttp:.2F.2Fgamedev.allusion.net.2Fdocs.2Fkos-current.2Fmatrix_8h.html_Dreamcast:_Basic_matrix_operations_.28KallistiOS.29.5D-40] 26.0 ^26.1 Dreamcast: Basic matrix operations (KallistiOS)

[:File:SH-4_Software_Manual.pdf_p211-41] File:SH-4 Software Manual.pdf, page 211

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA96_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28page_96.29.5D-43] Design of Digital Systems and Devices (page 96)

[:File:SH-4_Software_Manual.pdf_p151-44] File:SH-4 Software Manual.pdf, page 151

[:File:SH-4_Next-Generation_DSP_Architecture.pdf_p31-45] File:SH-4 Next-Generation DSP Architecture.pdf, page 31

[:File:DreamcastDevBoxSystemArchitecture.pdf_p-50] File:DreamcastDevBoxSystemArchitecture.pdf

[:File:TMP90PH44_datasheet.pdf_p-54] File:TMP90PH44 datasheet.pdf

[:File:HM62256B_datasheet.pdf_p-57] 33.0 ^33.1 File:HM62256B datasheet.pdf

[.5Bhttp:.2F.2Fwww.mamedb.com.2Fgame.2Fclubkrte.html_Club_Kart:_European_Session_.28MAME.29.5D-59] Club Kart: European Session (MAME)

[:File:XCF01S_datasheet.pdf_p-61] File:XCF01S datasheet.pdf

[:File:DreamcastDevBoxSystemArchitecture.pdf_p165-65] File:DreamcastDevBoxSystemArchitecture.pdf, page 165

[http:.2F.2Farchive.is.2FtZsMd-66] ttp://mc.pp.se/dc/pvr.html (archive.today)

[:File:DreamcastDevBoxSystemArchitecture.pdf_p96-67] File:DreamcastDevBoxSystemArchitecture.pdf, page 96

[:File:HM5264_datasheet.pdf_p-72] File:HM5264 datasheet.pdf

[:File:HY57V161610D_datasheet.pdf_p-75] File:HY57V161610D datasheet.pdf

[:File:CY2292_datasheet.pdf_p-80] File:CY2292 datasheet.pdf

[:File:M27C160_datasheet.pdf_p-81] File:M27C160 datasheet.pdf

[:File:AT93C46_datasheet.pdf_p-83] File:AT93C46 datasheet.pdf

[:File:S29GL-N_datasheet.pdf_p-85] File:S29GL-N datasheet.pdf

[.5Bhttp:.2F.2Ffarm6.staticflickr.com.2F5471.2F12172411045_18bfc5912f_c.jpg_Hideki_Sato_Sega_Inteview_.28Edge.29.5D-87] Hideki Sato Sega Inteview (Edge)

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_DIMM_board_and_GD-ROM_Sega_Naomi_DIMM_board_and_GD-ROM.5D-89] 46.0 ^46.1 Sega Naomi DIMM board and GD-ROM

[:File:M366S3323CT0_datasheet.pdf_p-91] File:M366S3323CT0 datasheet.pdf

[https:.2F.2Fweb.archive.org.2Fweb.2F19981206111041.2Fhttp:.2F.2Fwww.techweb.com.2Fwire.2Fstory.2FTWB19980923S0008-93] ttp://www.techweb.com/wire/story/TWB19980923S0008 (Wayback Machine: 1998-12-06 11:10)

[:File:NextGeneration_US_77.pdf_p61-94] Next Generation, "May 2001" (US; 2001-04-17), page 61

[:File:NextGeneration_US_76.pdf_p37-95] Next Generation, "April 2001" (US; 2001-03-20), page 37

[https:.2F.2Fweb.archive.org.2Fweb.2F20210205150032.2Fhttps:.2F.2Fwww.4gamer.net.2Fgames.2F999.2FG999905.2F20210126043.2F-96] ttps://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)

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Sega NAOMI 2

From Sega Retro

Contents

Hardware

Technical specifications

Graphics

Memory

Bandwidth

NAOMI 2 GD-ROM Specifications

Memory

Bandwidth

List of games

NAOMI 2

NAOMI 2 GD-ROM

NAOMI 2 Satellite Terminal

History

Production credits

Digital Manuals

Notes

References