Difference between revisions of "Sega NAOMI 2"

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==History==
 
==History==
−
[[wikipedia:Imagination Technologies|VideoLogic]]'s Elan, the T&L geometry GPU coprocessor used in the NAOMI 2, had been in development since 1998, when the original NAOMI arcade system and [[Dreamcast]] console launched.{{ref|https://web.archive.org/web/19981206111041/http://www.techweb.com/wire/story/TWB19980923S0008}} [[Yu Suzuki]] was involved in its development, insisting that it must have enough power to sustain in-game performance of at least 10 million polygons per second will all effects enabled.{{magref|nextgeneration|77|61}} It was also more affordable than the very expensive (and difficult to program) [[Sega Hikaru]] arcade system that preceded it.{{magref|nextgeneration|76|37}} The NAOMI 2 was nevertheless more powerful than home systems at the time.
+
[[wikipedia:Imagination Technologies|VideoLogic]]'s Elan, the T&L geometry GPU coprocessor used in the NAOMI 2, had been in development since 1998, when the original NAOMI arcade system and [[Dreamcast]] console launched.{{ref|https://web.archive.org/web/19981206111041/http://www.techweb.com/wire/story/TWB19980923S0008}} [[Yu Suzuki]] was involved in its development, insisting that it must have enough power to sustain in-game performance of at least 10 million polygons per second with all effects enabled.{{magref|nextgeneration|77|61}} It was also more affordable than the very expensive (and difficult to program) [[Sega Hikaru]] arcade system that preceded it.{{magref|nextgeneration|76|37}} The NAOMI 2 was nevertheless more powerful than home systems at the time.
  
 
==Production credits==
 
==Production credits==

Revision as of 05:30, 6 April 2024

Naomi 2.png
NAOMI2.jpg
Sega NAOMI 2
Manufacturer: Sega
Variants: Sega NAOMI 2 GD-ROM, Sega NAOMI 2 Satellite Terminal
Add-ons: GD-ROM
Release Date RRP Code
Arcade
World		 ? 171‑8082C




































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The Sega NAOMI 2 is an arcade board developed by Sega and is a successor to Sega NAOMI hardware. It was announced in 2000, with the first games utilising the technology shipping in 2001[1].

Hardware

The NAOMI 2 is significantly more powerful than the NAOMI, including a dual CPU setup, new T&L GPU, dual rasterizer GPU, increased memory, and faster bandwidth. This leads to games with much more polygons than a NAOMI game, rendered at much faster speeds, while the new T&L GPU adds advanced lighting and particle effects. It was also more affordable than the very expensive (and difficult to program) Sega Hikaru arcade system that preceded it. The NAOMI 2 was nevertheless more powerful than home systems at the time.

As with the NAOMI, the NAOMI 2 was also available in GD-ROM and Satellite Terminal variants. By using similar architecture to the original NAOMI, it is fully backwards compatible with its predecessor.

Technical specifications

  • Units: 128‑bit SIMD vector units with graphic functions, 2× 64‑bit floating‑point units, 2× 32‑bit fixed‑point units
  • Bus width: 128‑bit internal, 64‑bit external
  • Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
  • Fixed‑point performance: 360 MIPS
  • SH‑4 floating‑point performance: 1.4 GFLOPS
  • Note: With Elan used as geometry coprocessor, the SH‑4's 128‑bit SIMD matrix unit can be dedicated to game physics, artificial intelligence, collision detection, overall game code, or further enhancing graphics. CPU load is reduced by 90% with Elan.[5]
  • Internal CPU: 32‑bit ARM7 RISC CPU @ 45 MHz
  • CPU performance: 17 MIPS
  • PCM/ADPCM: 16‑bit depth, 48 kHz sampling rate (DVD quality), 64 channels
  • Other features: DSP, sound synthesizer
  • Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz[n 2]
  • Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6 MHz[n 3]
  • Sega 315‑6268 (Altera EPM7032AELC44‑10) CPLD @ 103.1 MHz[n 4]
  • Sega 315‑6269 (Altera MAX EPM7064AETC100‑10) CPLD @ 100 MHz[n 5]
  • Storage media: ROM cartridge
  • Extensions: communication, 4‑channel surround sound, PCI, MIDI, RS‑232C
  • Connection: JAMMA Video compliant

Graphics

  • GPU: 6 core processors (Elan, SH‑4 SIMD, 2× PowerVR2, 2 DAC)
  • Core units: 14 units (Elan, SH‑4 SIMD, 10 PowerVR2 cores, 2 DAC)
  • Clock rate: 200 MHz
  • GPU rasterizers: 2× NEC‑VideoLogic PowerVR2 @ 100 MHz
  • Revision: Dual PowerVR2 doubles rendering performance over NAOMI, which in turn had twice the rendering performance of the Dreamcast, as NAOMI revision has dual ISP cores in each PowerVR2[n 7]
  • Bus width: 128‑bit (external)
  • Cores: 2x TA (Tile Accelerators), 4x ISP (Image Synthesis Processors), 2x TSP (Texture & Shading Processor), 6x Triangle Setup FPU, 2x RAMDAC
  • Units: 176 rendering units (148 ISP units, 20 TSP units, 6 FPU units, 2 RAMDAC)
  • ISP units: 4x ISP Precalc Units, 4x ISP PE Arrays (128 PE processor elements), 4x Depth Accumulation Buffers, 4x Span RLC, 4x Span Sorters, 4x ISP Parameter Cache
  • TSP units: 2x TSP Precalc, 2x Parameter Cache, 2x Texture Cache, 2x Iterator Arrays, 2x Pixel Processing Engines, 2x Tile Accumulation Buffers, 2x Secondary Accumulation Buffers, 2x Combine & Bump Map Units, 2x Fog Units, 2x Alpha Blending Units[15]
  • Triangle Setup FPU: 6 FPU rendering units, 2.1 GFLOPS
  • 4x ISP Setup FPU: 100 MHz, 1457 MFLOPS, surface and culling processing for polygons, 28,571,428 polygons/sec[n 8]
  • 2x TSP Setup FPU: 100 MHz, 728 MFLOPS, shading and texture processing[16] for tiles processed by ISP[12]
  • Bus width: 48‑bit (2× 24‑bit)
  • Color depth: 32‑bit ARGB, 16,777,216 colors (24‑bit color) with 8‑bit (256 levels) alpha blending, YUV and RGB color spaces, color key overlay[21]
  • Display resolution: 31 kHz horizontal sync, 60 Hz refresh rate, JAMMA/VGA,[22] progressive scan
  • Single monitor: 496×384 to 800×608 pixels[23]
  • Dual monitor: 992×768 to 1600×608 pixels
  • 12 GTexels/s: Maximum fillrate for opaque polygons
  • 2 GTexel/s: Average fillrate for translucent and opaque polygons
  • 400 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
  • Textures per pass: 10 texture layers[10]
  • Floating-point performance: 11 GFLOPS
  • Elan: 7.5 GFLOPS geometry
  • SH-4 SIMD: 1.4 GFLOPS geometry
  • PowerVR2: 2.1 GFLOPS rendering
  • T&L geometry: 8.7 GFLOPS[n 13]
  • Matrix transformations: 240 million vertices/sec[n 14]
  • Perspective transformations: 210 million vertices/sec[n 15]
  • 1 light source: 110 million vertices/sec[n 16]
  • 4 light sources: 26 million vertices/sec[n 17]
  • 6 light sources: 18 million vertices/sec[n 18]
  • 100 million polygons/sec: 1 light source[10]
  • 26 million polygons/sec: 4 light sources, texture mapping
  • 10 million polygons/sec: 6 light sources, texture mapping

Memory

  • Overall memory: 304–584 MB (136 MB RAM, 168–448 MB ROM)
  • Video memory: 240–352 MB (96 MB RAM, 144–256 MB ROM)
  • Elan: 32 MB SDRAM (geometry/model data)
  • PowerVR2: 64 MB SDRAM[n 24]
  • 2000 format: 168–280 MB[n 26]
  • 2005 format: Up to 448 MB[n 27]

Bandwidth

  • Internal processor cache bandwidth:
  • SH4 cache: 3.2 GB/s[n 28]
  • GPU cache:
  • RAM/ROM memory bandwidth: 16.1 GB/s (15.1 GB/s system, 1 GB/s cartridge)
  • Video memory: 14.01 GB/s (13.01 GB/s VRAM, 900 MB/s ROM)
  • System RAM bandwidth: 10 GB/s[2]
  • Main RAM: 1.6 GB/s[n 34]
  • VRAM: 8.4 GB/s
  • System ROM bandwidth: 88 MB/s[2]
  • Cartridge ROM bandwidth: 900 MB/s[n 42]
  • Note: High‑speed access allows ROM to effectively be used as RAM, and textures streamed directly from ROM.[45]
  • Cartridge RAM bandwidth: 100 MB/s[n 43]

NAOMI 2 GD-ROM Specifications

The NAOMI GD‑ROM, released in 2001, is identical to the standard NAOMI, but uses GD‑ROM discs for storage instead of ROM cartridges. It comes with a DIMM Board, which is very similar to a ROM cartridge, but with RAM instead of ROM. When a game is installed, the GD‑ROM content is loaded onto the DIMM Board RAM, so that the game data runs from the DIMM Board rather than the GD‑ROM disc. The NAOMI 2 GD‑ROM specification includes the following differences:

  • Board composition: Motherboard + Daughter Board + DIMM Board
  • Storage media: GD‑ROM drive
  • GD‑ROM transfer rate: 1.8 MB/s (1800 KB/sec)

Memory

  • RAM: 392–648 MB (SDRAM)
  • Main RAM: 32 MB
  • VRAM: 96 MB
  • Sound RAM: 8 MB
  • DIMM RAM: 256–512 MB[46]
  • L2 cache: 256 KB
  • ROM: 26 MB
  • System ROM: 2048.25 KB[n 44]
  • DIMM ROM: 24 MB (EPROM)

Bandwidth

  • RAM bandwidth: 11–12 GB/s
  • Main RAM: 1.6 GB/s
  • VRAM: 8.4 GB/s
  • Sound RAM: 132 MB/s
  • SRAM: 44 MB/s
  • DIMM RAM: 1.1–2.13 GB/s[n 45]

List of games

NAOMI 2

NAOMI 2 GD-ROM

NAOMI 2 Satellite Terminal

History

VideoLogic's Elan, the T&L geometry GPU coprocessor used in the NAOMI 2, had been in development since 1998, when the original NAOMI arcade system and Dreamcast console launched.[48] Yu Suzuki was involved in its development, insisting that it must have enough power to sustain in-game performance of at least 10 million polygons per second with all effects enabled.[49] It was also more affordable than the very expensive (and difficult to program) Sega Hikaru arcade system that preceded it.[50] The NAOMI 2 was nevertheless more powerful than home systems at the time.

Production credits

Source:
Developer mentions[51]


Digital Manuals

  • EN Manual - Sega Corp (420-6644-01)

Notes

  1. ↑ [49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s[2] 49 units, 656‑bit internal, 224‑bit external, 125 MHz, 9.25 GB/s[2]]
  2. ↑ [42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,[6] 5.3 GB/s 42 units, 336‑bit (42× 8‑bit) internal, 120‑bit external,[6] 5.3 GB/s]
  3. ↑ [8‑bit,[7] 6 MB/s 8‑bit,[7] 6 MB/s]
  4. ↑ [2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,[8] 1.3403 GB/s 2 units, 104‑bit (2× 52‑bit) internal, 32‑bit (2× 16‑bit) external,[8] 1.3403 GB/s]
  5. ↑ [4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,[8] 2.6 GB/s 4 units, 208‑bit (4× 52‑bit) internal, 64‑bit (4× 16‑bit) external,[8] 2.6 GB/s]
  6. ↑ [75 floating-point operations per cycle 75 floating-point operations per cycle]
  7. ↑ [Scaled for high-end arcade technology,[11] with parallel ISP cores and increased PE processing elements within processor.[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.[14] Scaled for high-end arcade technology,[11] with parallel ISP cores and increased PE processing elements within processor.[12] NAOMI 2 has average fillrate of 2 gigapixels/sec, twice that of the NAOMI's average 1 gigapixel/sec fillrate,[13] which in turn is twice that of the Dreamcast's average 500 megapixels/sec fillrate.[14]]
  8. ↑ [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles[16][17] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 204 floating-point operations per 14 cycles[16][17]]
  9. ↑ [32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP) 32 pixels/cycle per ISP,1 pixel per PE (processor element), 128 PE (32 PE per ISP, 64 PE per PowerVR2), 6 gigapixels/sec per PowerVR2 (3.2 gigapixels/sec per ISP)]
  10. ↑ [20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP) 20 pixels per cycle, 6 PEs (processor elements) per pixel, 1 gigapixel per PowerVR2 (500 megapixels/sec per ISP)]
  11. ↑ [60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP) 60 layers depth, 4 pixels per cycle (2 pixels per PowerVR2), 32 PEs per pixel, 200 megapixels/sec per PowerVR2 (100 megapixels/sec per ISP)]
  12. ↑ [Same as pixel rendering fillrate Same as pixel rendering fillrate]
  13. ↑ [Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
    SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS) Elan: 7.5 GFLOPS (75 floating-point operations per cycle)
    SH‑4 SIMD: 180 MHz available (10% load, 20 MHz used), 1.26 GFLOPS (90% of 1.4 GFLOPS)]
  14. ↑ [Elan: 200 million vertices/sec (28 floating-point operations per transform,[24] 2 transforms per cycle)
    SH-4: 45 million vertices/sec (4 cycles per transform)[25] Elan: 200 million vertices/sec (28 floating-point operations per transform,[24] 2 transforms per cycle)
    SH-4: 45 million vertices/sec (4 cycles per transform)[25]]
  15. ↑ [Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,[24] 3 operations for perspective division),[26] 2 transforms per cycle
    SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,[25] 5 cycles perspective division),[26] 12 cycles division latency[27] Elan: 200 million vertices/sec, 31 floating-point operations per vertex (28 operations for matrix transform,[24] 3 operations for perspective division),[26] 2 transforms per cycle
    SH-4: 15 million vertices/sec, 12 cycles per vertex (4 cycles matrix transform,[25] 5 cycles perspective division),[26] 12 cycles division latency[27]]
  16. ↑ [Elan: 100 million vertices/sec (63 floating-point operations per vertex,[28] 1 vertex per cycle)
    SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)[29][30] Elan: 100 million vertices/sec (63 floating-point operations per vertex,[28] 1 vertex per cycle)
    SH-4: 12 million vertices/sec, 14 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix)[29][30]]
  17. ↑ [Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
    SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 20 million vertices/sec, 5 cycles per vertex (1 cycle transform, 1 cycle per light source)
    SH-4: 6 million vertices/sec, 29 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
  18. ↑ [Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
    SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix) Elan: 14 million vertices/sec, 7 cycles per vertex (1 cycle transform, 1 cycle per light source)
    SH-4: 4 million vertices/sec, 39 cycles per vertex (4 cycles matrix transformation, 5 cycles perspective division, 1 cycle per surface normal, 4 cycles per lighting matrix)]
  19. ↑ [432,206 bytes 432,206 bytes]
  20. ↑ [288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache[10] 288,322 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers, 256 KB L2 cache[10]]
  21. ↑ [94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer 94,208 bytes: 16.5 KB register memory, 49 KB ISP cache, 26 KB TSP cache, 512 bytes FIFO buffer]
  22. ↑ [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]
  23. ↑ [16,896 bytes: 512 bytes RAM, 16 KB ROM[32] 16,896 bytes: 512 bytes RAM, 16 KB ROM[32]]
  24. ↑ [2× 32 MB 2× 32 MB]
  25. ↑ [2 MB BIOS EPROM, 256 bytes EEPROM[2] 2 MB BIOS EPROM, 256 bytes EEPROM[2]]
  26. ↑ [24 MB EPROM,[34] 144–256 MB FlashROM/MROM 24 MB EPROM,[34] 144–256 MB FlashROM/MROM]
  27. ↑ [128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM[35] 128–448 MB FlashROM, 0–40 MB EPROM, 128 KB Flash PROM[35]]
  28. ↑ [128‑bit, 200 MHz 128‑bit, 200 MHz]
  29. ↑ [512‑bit, 100 MHz 512‑bit, 100 MHz]
  30. ↑ [2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,[37] 4x 1024-bit ISP PE Arrays,[12] 2x 64-bit TSP Texture Cache,[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer 2x 2304‑bit, 100 MHz: 2x 32-bit TA tile buffer,[36] 4x 32-bit ISP registers, 2x 32-bit TSP registers,[37] 4x 1024-bit ISP PE Arrays,[12] 2x 64-bit TSP Texture Cache,[38] 2x 32-bit TSP Tile Accumulation Buffer, 2x 32-bit Secondary Accumulation Buffer] (archive.today)
  31. ↑ [48‑bit, 35.4695 MHz 48‑bit, 35.4695 MHz]
  32. ↑ [32‑bit, 67 MHz 32‑bit, 67 MHz]
  33. ↑ [656‑bit, 125 MHz 656‑bit, 125 MHz]
  34. ↑ [128‑bit, 100 MHz[39] 128‑bit, 100 MHz[39]]
  35. ↑ [512‑bit, 100 MHz[9] 512‑bit, 100 MHz[9]]
  36. ↑ [128‑bit, 125 MHz[40] 128‑bit, 125 MHz[40]]
  37. ↑ [16‑bit, 66 MHz 16‑bit, 66 MHz]
  38. ↑ [16‑bit, 22 MHz[33] 16‑bit, 22 MHz[33]]
  39. ↑ [8‑bit, 6 MHz[7] 8‑bit, 6 MHz[7]]
  40. ↑ [16‑bit, 40 MHz[41][42] 16‑bit, 40 MHz[41][42]]
  41. ↑ [2× 16‑bit, 2 MHz[43] 2× 16‑bit, 2 MHz[43]]
  42. ↑ [50 MHz[44] 50 MHz[44]]
  43. ↑ [16‑bit, 50 MHz 16‑bit, 50 MHz]
  44. ↑ [24 MB BIOS EPROM, 256 bytes EEPROM 24 MB BIOS EPROM, 256 bytes EEPROM]
  45. ↑ [1/2× 64‑bit, 133 MHz[46][47] 1/2× 64‑bit, 133 MHz[46][47]]

References

  1. ↑ 1.0 1.1 http://www.sega.co.jp/sega/corp/news/nr000921_3.html (Wayback Machine: 2000-12-03 04:43)
  2. ↑ 2.0 2.1 2.2 2.3 2.4 2.5 2.6 Sega NAOMI / NAOMI 2 (MAME)
  3. ↑ 3.0 3.1 DC-UK, "December 2000" (UK; 2000-10-23), page 41
  4. ↑ File:SH-4 Software Manual.pdf
  5. ↑ 5.0 5.1 Press release: 2000-09-21: Sega Announces NAOMI2 Next Generation Arcade Systems Using Imagination Technologies’ PowerVR Graphics Architecture
  6. ↑ File:EPF8452A datasheet.pdf
  7. ↑ 7.0 7.1 7.2 File:EPC1064 datasheet.pdf
  8. ↑ 8.0 8.1 File:EPM7032AE datasheet.pdf
  9. ↑ 9.0 9.1 File:UPD4564323 datasheet.pdf
  10. ↑ 10.0 10.1 10.2 10.3 NAOMI 2 Specifications (May 31, 2001)
  11. ↑ File:PowerVR.pdf, page 2
  12. ↑ 12.0 12.1 12.2 File:PowerVR.pdf, page 3
  13. ↑ Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM
  14. ↑ Edge, "January 1999" (UK; 1998-12-23), page 11
  15. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 110
  16. ↑ 16.0 16.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 95
  17. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 203
  18. ↑ JAMMA 2000: NAOMI 2 Revealed (September 20, 2000)
  19. ↑ File:NAOMI 1998 Press Release JP.pdf
  20. ↑ File:BU142 datasheet.pdf
  21. ↑ http://www3.sharkyextreme.com/hardware/reviews/video/neon250/2.shtml (Wayback Machine: 2007-08-11 10:20)
  22. ↑ Sega Naomi Universal
  23. ↑ Dreamcast Video (KallistiOS)
  24. ↑ 24.0 24.1 Design of Digital Systems and Devices (page 95)
  25. ↑ 25.0 25.1 File:SH-4 Next-Generation DSP Architecture.pdf, page 12
  26. ↑ 26.0 26.1 Dreamcast: Basic matrix operations (KallistiOS)
  27. ↑ File:SH-4 Software Manual.pdf, page 211
  28. ↑ Design of Digital Systems and Devices (page 96)
  29. ↑ File:SH-4 Software Manual.pdf, page 151
  30. ↑ File:SH-4 Next-Generation DSP Architecture.pdf, page 31
  31. ↑ File:DreamcastDevBoxSystemArchitecture.pdf
  32. ↑ File:TMP90PH44 datasheet.pdf
  33. ↑ 33.0 33.1 File:HM62256B datasheet.pdf
  34. ↑ Club Kart: European Session (MAME)
  35. ↑ File:XCF01S datasheet.pdf
  36. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 165
  37. ↑ http://mc.pp.se/dc/pvr.html (archive.today)
  38. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 96
  39. ↑ File:HM5264 datasheet.pdf
  40. ↑ File:HY57V161610D datasheet.pdf
  41. ↑ File:CY2292 datasheet.pdf
  42. ↑ File:M27C160 datasheet.pdf
  43. ↑ File:AT93C46 datasheet.pdf
  44. ↑ File:S29GL-N datasheet.pdf
  45. ↑ Hideki Sato Sega Inteview (Edge)
  46. ↑ 46.0 46.1 Sega Naomi DIMM board and GD-ROM
  47. ↑ File:M366S3323CT0 datasheet.pdf
  48. ↑ http://www.techweb.com/wire/story/TWB19980923S0008 (Wayback Machine: 1998-12-06 11:10)
  49. ↑ Next Generation, "May 2001" (US; 2001-04-17), page 61
  50. ↑ Next Generation, "April 2001" (US; 2001-03-20), page 37
  51. ↑ https://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)


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