Sega Dreamcast/Technical specifications

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Technical specifications for the Sega Dreamcast.

CPU

  • Operating frequency: 200 MHz
  • Features: RISC, 2-way Superscalar,[3][1] parallel pipelining[4]
  • Units: 128‑bit SIMD vector unit with graphic functions, 64‑bit floating‑point unit, 32‑bit fixed‑point unit, DMA controller[2] (frees CPU for other tasks),[5] interrupt controller[2]
  • 128‑bit vector graphic computational engine (SIMD) @ 200 MHz: Vector unit, geometry processor, DSP, graphic functions,[2][6] 3D capabilities,[5] calculates T&L geometry and lighting of polygons, creates display lists of polygons for tiling, DMA allows SH4 access to VRAM and PowerVR2 access to Main RAM, store queue mechanism (allowing high‑speed packet transfers between Main RAM and VRAM)[7]
  • Bus width: 128‑bit internal, 64‑bit external
  • Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
  • Performance:

Graphics

Graphical specifications of the Dreamcast:[9][7][10]

  • GPU: 2 graphics processors (SH‑4 SIMD, CLX2)
  • Cores: 6 cores (SH‑4 SIMD, 5 CLX2 cores)
  • GPU Geometry Processor: Hitachi SH‑4 SIMD @ 200 MHz (1.4 GFLOPS)
  • GPU Rasterizer: NEC‑VideoLogic PowerVR CLX2 (PVR2DC/HOLLY) @ 100 MHz (PowerVR2 series)
  • CLX2 Cores: Tile Accelerator (TA), Image Synthesis Processor (ISP), Texture & Shading Processor (TSP), Triangle Setup FPU, RAMDAC[11]
  • CLX2 units: 50 rendering units (37 ISP units, 10 TSP units, 2 FPU units, 1 RAMDAC)
  • TA Tile Accelerator: Tile renderer, partitions infinite strip polygon data, divides polygons into tiles, performs tile clipping, generates object lists, retrieves display lists from SH4 (through store queues and DMA), generates ISP/TSP parameters
  • ISP Image Synthesis Processor: Rasterizer, depth‑sorting, parallel‑processing of tiles/pixels/polygons at high speeds, reduces bandwidth requirements[14]
  • 37 ISP units: ISP Precalc Unit, ISP PE Array (32 PE), Depth Accumulation Buffer, Span RLC, Span Sorter, ISP Parameter Cache[15]
  • ISP PE Array: 32 processor elements (PE), on-chip depth sorting, on-chip Z-buffering, 3D processing of 32 pixels/cycle per PE (1024-bit), 32-bit Z-buffer depth data processing[gn 4]
  • ISP Parameter Cache: 12 KB
  • Span RLC: RLE tile/polygon compression, 32 pixels/cycle, 32-bit[gn 5]
  • TSP Texture & Shading Processor: Shader and texture‑mapping unit[gn 6]
  • 10 TSP units: TSP Precalc, Parameter Cache, Texture Cache, Iterator Array, Pixel Processing Engine, Tile Accumulation Buffer, Secondary Accumulation Buffer, Combine & Bump Map Unit, Fog Unit, Alpha Blending Unit[18]
  • Pixel Processing Engine: Texturing/Shading for 32-pixel data processed by ISP[16]
  • TSP Parameter Cache: 12 KB[15]
  • Texture Cache: 1 KB (64-bit), VQ texture compression/decompression
  • Tile Accumulation Buffer: 4 KB (32-bit),[19] 32×32 pixels[20]
  • Secondary Accumulation Buffer: 4 KB (32-bit),[19] 32×32 pixels
  • Triangle Setup FPU: 2 FPU rendering units, 728 MFLOPS
  • ISP Setup FPU: 100 MHz, 364 MFLOPS, surface and culling processing for polygons, 7,142,857 polygons/sec[gn 7]
  • TSP Setup FPU: 100 MHz, 364 MFLOPS, shading and texture processing[21] for tiles processed by ISP[16]
  • Internal resolution: 320×240 to 1600×1200 pixels[23]
  • Texture map resolutions: 8×8 to 2048×2048 texels[25]
  • Refresh rate: 30–60 Hz (NTSC/PAL60), 25–50 Hz (PAL50)[44]
  • Maximum frame rate: 60 FPS (NTSC/PAL60), 50 FPS (PAL50)
  • Strip/Tile buffer: 32×32×16‑bit (4 KB) to 32×32×32‑bit (8 KB) in local tile buffer cache memory[7]
  • Full framebuffer: 320×240×16-bit (300 KB) to 1600×1200×24‑bit (5625 KB) or 2048×2048×16‑bit (8 MB) in VRAM (optional)[47]
  • Note: Due to deferred rendering, framebuffer only needs to be filled once per fram[gn 9]
  • VRAM: 8 MB (unified framebuffer and texture memory, effectively 21–63 MB with texture compression)[48][7]
  • Framebuffer: 300–5625 KB (optional)[gn 10]
  • Polygons: Stored in double-buffered display lists,[49][50] 22 bytes per shaded triangle,[gn 11] 31 bytes per textured triangle,[gn 12] 36 bytes per bump-mapped triangle,[gn 13] 38 bytes per volume-modified triangle,[gn 14] 96 bytes per sprite[gn 15][51]
  • Textures: 32 KB[gn 16] to 8 MB (effectively 21–63 MB with texture compression),[27]Average 5 MB[52] (effectively 20–30 MB with texture compression)[26]

32 bytes[gn 17] to 386 KB[gn 18] or 1026 KB[gn 19] per texture

  • VRAM bandwidth: 800 MB/s (effectively up to 2.1–6.3 GB/s with texture compression)
  • Note: Main RAM also used to store polygon display lists. Textures transferred directly to VRAM. Main RAM can also optionally be used to store textures.
    • Floating-Point Performance: 2.1 GFLOPS
    • SH-4 SIMD: 1.4 GFLOPS geometry
    • CLX2: 728 MFLOPS rendering
    • 3.2 GPixels/s: Maximum fillrate for opaque polygons[gn 20]
    • 500 MPixels/s: Average fillrate for translucent and opaque polygons[53][gn 21]
    • 100 MPixels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60[gn 22]
    • 100 MPixels/s to 3.2 GPixels/s, depending on translucency and depth of polygons[gn 23]
    • 3.2 GTexels/s: Maximum fillrate for opaque polygons
    • 500 MTexels/s: Average fillrate for translucent and opaque polygons
    • 100 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
    • Matrix transformations: 50 million vertices/s[gn 25]
    • Perspective transformations: 16.6 million vertices/sec,[gn 26] 16 million polygons/s[gn 27]
    • 1 light source: 14.2 million vertices/s,[gn 28] 14 million polygons/s[gn 29][3]
    • 4 light sources: 6.89 million vertices/s,[gn 30] 6.8 million polygons/s
    • 16 million vertices/s[gn 31]
    • 7.1 million polygons/s: Lighting, Gouraud shading[gn 32]
    • 7–7.1 million polygons/s: Lighting, texture mapping, Gouraud shading[gn 33]
    • 7 million polygons/s: Lighting, texture mapping, shadows[23][gn 34]
    • 7 million polygons/s: Lighting, texture mapping, trilinear filtering[63][gn 34]
    • 5–6.4 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping[gn 35]
    • 4.13 million polygons/s: Lighting, texture mapping, anisotropic filtering[gn 36]
    • 3.12 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping, anisotropic filtering, translucent polygons[gn 37]
    • 2D sprite capabilities: Sprites rendered as textured translucent quad polygons[65]
    • Colors per sprite: 16 colors (4-bit color) to 16,777,216 colors (24-bit color)[66]
    • Sprite sizes: 8×8 texels (224 bytes) to 2048×2048 texels (1026.2 KB)[24][27]
    • Sprite fillrate: 100 MTexels/s
    • Maximum sprites per frame: 26,041 sprites (8×8, 60 FPS), 31,250 sprites (8×8, 50 FPS)
    • Maximum texels per scanline: 6944 texels (NTSC/PAL60), 8333 texels (PAL50)
    • Maximum sprites per scanline: 868 sprites (NTSC/PAL60), 1041 sprites (PAL50)
    • Full Motion Video: MPEG decoding, video compression, 320×240 to 640×320 and 320×480 video resolutions, 3D polygons can be superimposed over FMV video[3]

    Notes

    1. ↑ [2 instructions per cycle[8] 2 instructions per cycle[8]]
    2. ↑ [7 floating-point operations per cycle 7 floating-point operations per cycle]
    3. ↑ [32-bit,[12] 2397 bytes[13] 32-bit,[12] 2397 bytes[13]]
    4. ↑ [3 cycles/polygon, 1 tile/cycle[16][17] 3 cycles/polygon, 1 tile/cycle[16][17]]
    5. ↑ [3.2 GPixels/s 3.2 GPixels/s]
    6. ↑ [Avoids shading/texturing overdrawn pixels/tiles and back‑facing polygons to maximize bandwidth for on‑screen pixels/tiles and front‑facing polygons, perspective correction for all texture/shading elements (including fog and alpha blending)[14] Avoids shading/texturing overdrawn pixels/tiles and back‑facing polygons to maximize bandwidth for on‑screen pixels/tiles and front‑facing polygons, perspective correction for all texture/shading elements (including fog and alpha blending)[14]]
    7. ↑ [14 cycles per polygon, 51 floating-point operations per polygon, 51 floating-point operations per 14 cycles[21][22] 14 cycles per polygon, 51 floating-point operations per polygon, 51 floating-point operations per 14 cycles[21][22]]
    8. ↑ [32 pixels per cycle[3][14] 32 pixels per cycle[3][14]] (Wayback Machine: 2000-08-23 20:47)
    9. ↑ [For opaque polygons, while translucent polygons can overdraw with up to 100 MPixels/s (200–300 MB/s) For opaque polygons, while translucent polygons can overdraw with up to 100 MPixels/s (200–300 MB/s)]
    10. ↑ [Average 1200 KB (640×480, 16-bit color, double-buffered) Average 1200 KB (640×480, 16-bit color, double-buffered)]
    11. ↑ [Flat/Gouraud shading, 43 bytes double-buffered Flat/Gouraud shading, 43 bytes double-buffered]
    12. ↑ [Gouraud shading, 62 bytes double-buffered Gouraud shading, 62 bytes double-buffered]
    13. ↑ [Textured, Gouraud shading, bump mapping, 72 bytes double-buffered Textured, Gouraud shading, bump mapping, 72 bytes double-buffered]
    14. ↑ [Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered]
    15. ↑ [Sprite, quad, 192 bytes double-buffered Sprite, quad, 192 bytes double-buffered]
    16. ↑ [8×8 texture, 16 colors 8×8 texture, 16 colors]
    17. ↑ [8×8×4-bit 8×8×4-bit]
    18. ↑ [1024×1024×24-bit[27][25] 1024×1024×24-bit[27][25]]
    19. ↑ [2048×2048×16-bit[25] 2048×2048×16-bit[25]]
    20. ↑ [32 pixels per cycle,[14] 1 pixel per PE (processor element)[16][17] 32 pixels per cycle,[14] 1 pixel per PE (processor element)[16][17]]
    21. ↑ [5 pixels per cycle, 6 PEs (processor elements) per pixel 5 pixels per cycle, 6 PEs (processor elements) per pixel]
    22. ↑ [60 layers depth, 1 pixel per cycle, 32 PEs per pixel 60 layers depth, 1 pixel per cycle, 32 PEs per pixel]
    23. ↑ [1–60 layers depth, 1–32 pixels per cycle,[10] 1–32 PEs per pixel 1–60 layers depth, 1–32 pixels per cycle,[10] 1–32 PEs per pixel]
    24. ↑ [Same as pixel rendering fillrate Same as pixel rendering fillrate]
    25. ↑ [4 cycles per matrix transformation[55] 4 cycles per matrix transformation[55]]
    26. ↑ [12 cycles per vertex (12 cycles division latency)[56]
      • 4 cycles matrix transformation[55]
      • 5 cycles perspective division: 2 multiplies, 1 divide, 2 FLDI1[57] (1 MAC per cycle,[58] 1 divide per cycle,[56] 1 cycle per FLDI1)[59] 12 cycles per vertex (12 cycles division latency)[56]
      • 4 cycles matrix transformation[55]
      • 5 cycles perspective division: 2 multiplies, 1 divide, 2 FLDI1[57] (1 MAC per cycle,[58] 1 divide per cycle,[56] 1 cycle per FLDI1)[59]]
    27. ↑ [N triangle strips per N+2 vertices[60] N triangle strips per N+2 vertices[60]]
    28. ↑ [14 cycles per vertex: 4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix[61][54][62] 14 cycles per vertex: 4 cycles matrix transformation, 5 cycles perspective division, 1 cycle surface normal, 4 cycles lighting matrix[61][54][62]]
    29. ↑ [N triangle strips per N+2 vertices N triangle strips per N+2 vertices]
    30. ↑ [29 cycles per vertex: 4 cycles matrix transformation, 5 cycles perspective division, 4 surface normals (4 cycles), 4 lighting matrices (16 cycles) 29 cycles per vertex: 4 cycles matrix transformation, 5 cycles perspective division, 4 surface normals (4 cycles), 4 lighting matrices (16 cycles)]
    31. ↑ [14 ISP FPU cycles per 3 vertices,[21] 192 pixels per vertex 14 ISP FPU cycles per 3 vertices,[21] 192 pixels per vertex]
    32. ↑ [14 ISP FPU cycles per polygon,[21] 119,000–187,000 polygons per scene, 450 pixels per polygon 14 ISP FPU cycles per polygon,[21] 119,000–187,000 polygons per scene, 450 pixels per polygon]
    33. ↑ [116,000–130,326 polygons per scene, 70 texels per polygon 116,000–130,326 polygons per scene, 70 texels per polygon]
    34. ↑ 34.0 34.1 [116,000–116,667 polygons per scene, 71 texels per polygon 116,000–116,667 polygons per scene, 71 texels per polygon]
    35. ↑ [83,000–107,736 polygons per scene, 78–100 texels per polygon 83,000–107,736 polygons per scene, 78–100 texels per polygon]
    36. ↑ [68,832 polygons per scene,[64] 121 texels per polygon 68,832 polygons per scene,[64] 121 texels per polygon]
    37. ↑ [50,000–56,000 polygons per scene, 32 texels per polygon 50,000–56,000 polygons per scene, 32 texels per polygon]

    Memory

    • System ROM: 2 MB[9]
    • Flash Memory: 128 KB[7]
    • GD-ROM Drive: 12× maximum speed (when running in Constant Angular Velocity mode)[9][7]
    • Disc formats: GD‑ROM, CD‑ROM, CD‑DA, , Photo CD, Video CD, CD Extra, CD+G, CD+EG
    • Storage capacity: 1 GB per GD‑ROM, 656 MB per CD‑ROM

    Bandwidth

    • Internal Processor Cache Bandwidth: 18.8 GB/s[mn 12]
    • System ROM Bandwidth: 20 MB/s[mn 16]
    • Transmission Bandwidth:[72]
    • SH4 <‑> CLX2 — 800 MB/s[mn 17]
    • SH4IF <-> PVRIF — 400 MB/s[mn 18]
    • SH4 <-> Root Bus — 200 MB/s[mn 19]
    • GD‑ROM Drive: 1.8 MB/s transfer rate, 250 milliseconds access time

    Notes

    1. ↑ Hyundai HY57V161610D[67]
      • Can be used for storing textures and polygon display lists, accessible by SH4 and PowerVR2 (via SH4 DMA)[7]
    2. ↑ [Unified framebuffer and texture memory[48]
      • Accessible by Power VR2 and SH4 (via DMA and store queues)
      Unified framebuffer and texture memory[48]
      • Accessible by Power VR2 and SH4 (via DMA and store queues)]
    3. ↑ [93,518 bytes 93,518 bytes]
    4. ↑ [26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache,[68] 1538 bytes registers 26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache,[68] 1538 bytes registers]
    5. ↑ [34,560 bytes:
      • Register memory: 8.25 KB[69] (2397 bytes TA tile buffer,[13][12] 509 bytes fog table, 4093 bytes palette RAM)[70]
      • ISP cache: 12.25 KB (12 KB ISP Parameter Cache,[15] 128 bytes Depth Accumulation Buffer, 1024-bit ISP PE Array)[16]
      • TSP cache: 13 KB (4 KB TSP Parameter Cache,[15] 1 KB Texture Cache,[14] 4 KB Tile Accumulation Buffer,[20][19] 4 KB Secondary Accumulation Buffer)[19]
      • FIFO buffer: 256 bytes
      34,560 bytes:
      • Register memory: 8.25 KB[69] (2397 bytes TA tile buffer,[13][12] 509 bytes fog table, 4093 bytes palette RAM)[70]
      • ISP cache: 12.25 KB (12 KB ISP Parameter Cache,[15] 128 bytes Depth Accumulation Buffer, 1024-bit ISP PE Array)[16]
      • TSP cache: 13 KB (4 KB TSP Parameter Cache,[15] 1 KB Texture Cache,[14] 4 KB Tile Accumulation Buffer,[20][19] 4 KB Secondary Accumulation Buffer)[19]
      • FIFO buffer: 256 bytes]
    6. ↑ [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers,[9] 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers,[9] 4 bytes FIFO buffer]
    7. ↑ [4 buses, 160-bit bus width[9] 4 buses, 160-bit bus width[9]]
    8. ↑ [64‑bit, 100 MHz[71] 64‑bit, 100 MHz[71]]
    9. ↑ [64‑bit, 100 MHz,[72] 64‑bit, 100 MHz,[72]]
    10. ↑ [16‑bit, 66 MHz 16‑bit, 66 MHz]
    11. ↑ [16‑bit 16‑bit]
    12. ↑ [384‑bit 384‑bit]
    13. ↑ [128‑bit, 200 MHz 128‑bit, 200 MHz]
    14. ↑ [1248‑bit, 100 MHz:
      • Register memory: 1.2 GB/s (32-bit ISP registers, 32-bit TSP registers,[37] 32-bit TA tile buffer)[12]
      • ISP PE Array: 12.8 GB/s (1024-bit)[16]
      • TSP cache: 1.6 GB/s (64-bit Texture Cache,[14] 32-bit Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer)
      1248‑bit, 100 MHz:
      • Register memory: 1.2 GB/s (32-bit ISP registers, 32-bit TSP registers,[37] 32-bit TA tile buffer)[12]
      • ISP PE Array: 12.8 GB/s (1024-bit)[16]
      • TSP cache: 1.6 GB/s (64-bit Texture Cache,[14] 32-bit Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer)]
    15. ↑ [32‑bit, 67 MHz 32‑bit, 67 MHz]
    16. ↑ [16‑bit, 10 MHz 16‑bit, 10 MHz]
    17. ↑ [64‑bit, 100 MHz 64‑bit, 100 MHz]
    18. ↑ [32‑bit, 100 MHz 32‑bit, 100 MHz]
    19. ↑ [32‑bit, 50 MHz 32‑bit, 50 MHz]

    BIOS

    BIOS Revisions
    BIOS Version Machine Download
    1.004 Sega Dreamcast (Commercial-Early) 1.004 (Japan) (info) (912 kB)
    1.01d Sega Dreamcast (Commercial) 1.01d (North America) (info) (885 kB)
    1.01d (Europe) (info) (886 kB)
    1.01d (Japan) (info) (885 kB)
    1.011 Sega Dreamcast (HKT-0120 Devbox) 1.011 (HKT-0120 Devbox) (info) (991 kB)

    Other specifications

    • Operating Systems:
    • Dimensions: 189mm x 195mm x 76mm (7 7/16" x 7 11/16" x 3")
    • Weight: 1.9kg (4.4lbs)
    • Input devices: (4 custom controller ports)

    References

    1. ↑ 1.0 1.1 File:SH-4 Software Manual.pdf
    2. ↑ 2.0 2.1 2.2 2.3 File:SH-4 datasheet.pdf
    3. ↑ 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 http://computer.org/micro/articles/dreamcast_2.htm (Wayback Machine: 2000-08-23 20:47)
    4. ↑ File:SH-4 Software Manual.pdf, page 187
    5. ↑ 5.0 5.1 5.2 Gamers' Republic, "August 1998" (US; 1998-07-21), page 29
    6. ↑ File:SH-4 Next-Generation DSP Architecture.pdf
    7. ↑ 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 File:DreamcastDevBoxSystemArchitecture.pdf
    8. ↑ File:SH-4 Software Manual.pdf, page 5
    9. ↑ 9.0 9.1 9.2 9.3 9.4 9.5 File:Dreamcast Hardware Specification Outline.pdf
    10. ↑ 10.0 10.1 File:PowerVR2DCFeaturesUnderWindowsCE.pdf
    11. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 94
    12. ↑ 12.0 12.1 12.2 File:DreamcastDevBoxSystemArchitecture.pdf, page 165
    13. ↑ 13.0 13.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 101
    14. ↑ 14.0 14.1 14.2 14.3 14.4 14.5 File:DreamcastDevBoxSystemArchitecture.pdf, page 96
    15. ↑ 15.0 15.1 15.2 15.3 15.4 PC 3D Graphics Accelerators FAQ: VideoLogic PowerVR
    16. ↑ 16.00 16.01 16.02 16.03 16.04 16.05 16.06 16.07 16.08 16.09 16.10 File:PowerVR.pdf, page 3
    17. ↑ 17.0 17.1 17.2 17.3 File:Patent US20030025695.pdf
    18. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 110
    19. ↑ 19.0 19.1 19.2 19.3 File:DreamcastDevBoxSystemArchitecture.pdf, page 111
    20. ↑ 20.0 20.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 127
    21. ↑ 21.0 21.1 21.2 21.3 File:DreamcastDevBoxSystemArchitecture.pdf, page 95
    22. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 203
    23. ↑ 23.0 23.1 23.2 http://segatech.com/technical/gpu/index.html (archive.today)
    24. ↑ 24.0 24.1 24.2 File:DreamcastDevBoxSystemArchitecture.pdf, page 98
    25. ↑ 25.0 25.1 25.2 25.3 25.4 File:DreamcastDevBoxSystemArchitecture.pdf, page 144
    26. ↑ 26.0 26.1 Hideki Sato Sega Interview (Edge)
    27. ↑ 27.0 27.1 27.2 27.3 File:PowerVR2DCFeaturesUnderWindowsCE.pdf, page 9
    28. ↑ 28.0 28.1 28.2 SEGA Dreamcast: Programming Hints
    29. ↑ File:PowerVR2DCFeaturesUnderWindowsCE.pdf, page 11
    30. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 120
    31. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 116
    32. ↑ 32.0 32.1 32.2 32.3 File:Dreamcast Hardware Specification Outline.pdf, page 22
    33. ↑ Optimizing Dreamcast Microsoft Direct3D Performance (1999-03-01) (Microsoft)
    34. ↑ 34.0 34.1 File:PowerVR.pdf, page 4
    35. ↑ Tiling Accelerator Notes
    36. ↑ Zombie Revenge (21 January 2000)
    37. ↑ 37.0 37.1 PowerVR (Dreamcast Hardware)
    38. ↑ Dreamcast Comparison
    39. ↑ Quake III Arena vs Unreal Tournament (IGN)
    40. ↑ Dreamcast homebrew - winter terrain and light bloom
    41. ↑ Dreamcast homebrew engine: More dynamic shadows and lighting
    42. ↑ DF Retro: Shenmue - A Game Ahead Of Its Time (Digital Foundry)
    43. ↑ http://segatech.com/archives/february1998.html (Wayback Machine: 2001-04-14 02:13)
    44. ↑ 44.0 44.1 File:Dreamcast Hardware Specification Outline.pdf, page 23
    45. ↑ http://www3.sharkyextreme.com/hardware/reviews/video/neon250/2.shtml (Wayback Machine: 2007-08-11 10:20)
    46. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 13
    47. ↑ 47.0 47.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 93
    48. ↑ 48.0 48.1 File:Dreamcast Hardware Specification Outline.pdf, page 18
    49. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 102
    50. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 152
    51. ↑ 51.0 51.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 199
    52. ↑ http://segatech.com/technical/polygons/index.html (Wayback Machine: 2001-03-06 00:59)
    53. ↑ Edge, "January 1999" (UK; 1998-12-23), page 11
    54. ↑ 54.0 54.1 File:SH-4 Software Manual.pdf, page 151
    55. ↑ 55.0 55.1 File:SH-4 Next-Generation DSP Architecture.pdf, page 12
    56. ↑ 56.0 56.1 File:SH-4 Software Manual.pdf, page 211
    57. ↑ Dreamcast: Basic matrix operations (KallistiOS)
    58. ↑ File:SH-4 Next-Generation DSP Architecture.pdf, page 4
    59. ↑ File:SH-4 Software Manual.pdf, page 295
    60. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 91
    61. ↑ Design of Digital Systems and Devices (page 96)
    62. ↑ File:SH-4 Next-Generation DSP Architecture.pdf, page 31
    63. ↑ Vintage Game Consoles: An Inside Look at Apple, Atari, Commodore, Nintendo, and the Greatest Gaming Platforms of All Time (Page 277)
    64. ↑ Homebrew Test
    65. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 103
    66. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 138
    67. ↑ File:HY57V161610D datasheet.pdf
    68. ↑ File:SH-4 Software Manual.pdf, page 25
    69. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 17
    70. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 37
    71. ↑ File:Dreamcast Hardware Specification Outline.pdf, page 14
    72. ↑ 72.0 72.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 42
    73. ↑ File:DreamcastDevBoxSystemArchitecture.pdf, page 49
    74. ↑ File:Dreamcast Hardware Specification Outline.pdf, page 6


    Sega Dreamcast
    Topics Technical specifications (Hardware comparison) | History (Development | Release | Decline and legacy | Internet) | List of games | Magazine articles | Promotional material | Merchandise
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    Online Services/Add-ons Dreamarena | SegaNet | WebTV for Dreamcast | Modem | Modular Cable | Modular Extension Cable | Broadband Adapter | Dreamphone
    Connector Cables Onsei Setsuzoku Cable | RF Adapter | Scart Cable | S Tanshi Cable | Stereo AV Cable | VGA Box

    Dreamcast MIDI Interface Cable | Neo Geo Pocket/Dreamcast Setsuzoku Cable | Taisen Cable

    Misc. Hardware Action Replay CDX | Code Breaker | Kiosk | MP3 DC | MP3 DC Audio Player | Official Case | Treamcast
    Third-party accessories Controllers | Controller converters | Miscellaneous
    Unreleased Accessories DVD Player | Zip Drive | Swatch Access for Dreamcast | VMU MP3 Player
    Arcade Variants NAOMI | Atomiswave | Sega Aurora
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