Difference between revisions of "Sega Model 1"

From Sega Retro
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| arcade_code_jp=837-8886171{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/model1.cpp Sega Model 1 Hardware Overview (MAME)]}}
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| system_code_jp=837-8886171{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/model1.cpp Sega Model 1 Hardware Overview (MAME)]}}
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| system_date_uk=1992
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| arcade_rrp_uk=6,000{{fileref|MeanMachinesSega26UK.pdf|page=18}}
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| system_rrp_uk=6,000{{fileref|MeanMachinesSega26UK.pdf|page=18}}
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| arcade_code_eu=837-8886171
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| system_code_uk=837-8886171
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==References==
 
==References==
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[[Category:Sega Model series]]
 
[[Category:Sega Model series]]

Revision as of 22:23, 14 July 2018

Model1 board.jpg
Sega Model 1
Manufacturer: Sega
Release Date RRP Code
Arcade
JP		 ¥? 837-8886171[1]
Arcade
UK		 £6,000[2] 837-8886171
Arcade
World		 ? 837-8886171





































The Sega Model 1 is an arcade system board that was released by Sega in 1992. It is the successor to the Sega System 32 (released in 1990). While earlier Sega hardware was capable of handling 3D polygons (such as the Mega Drive, released in 1988), the Model 1 was Sega's first hardware specifically designed for 3D polygon graphics.

Originally, the Model 1 was simply known as the CG Board, but was retroactively given the Model 1 name after work on the Model 2 began. The Model 1 was succeeded by the Sega Model 2 (released in 1993). Both the Model 1 and Model 2 were eventually succeeded by the Sega Model 3.

Hardware

It began development in 1990,[3] with Yu Suzuki's Sega AM2 team involved in its development from the drawing board.[4] The Model 1 was intended to compete with Namco's System 21; Namco was then the market leader in polygonal 3D video games, with titles such as Galaxian³ and Starblade.[5] The Model 1 was eventually released in 1992, debuting with Virtua Racing. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform.

“ Dedicated 3D processors didn’t exist yet, and so I had to manually write a 3D graphics engine that would compress and process things faster. Just using assembly language. Now, of course, everyone writes in C++, but back then there was no other choice than machine code, otherwise we wouldn't be able to make everything fast enough. „

— Yu Suzuki [6]

Unlike the Model 2, Lockheed Martin was not involved with the development of the Model 1, but it was developed internally at Sega, before Lockheed Martin became involved with the development of the Sega Model 2, according to former Lockheed Martin employee, Real3D's Jon Lenyo, in 1998.[3]

Like the Model 2, Fujitsu was involved with the development of the Model 1. They provided the DSP coprocesors, which were modified by Sega with custom microcode for hardware T&L capabilities;[7] hardware T&L would not appear on consumer home systems for many years. Fujitsu also provided several other components, including the tilemap generator chip, the DMA controllers, and several memory chips.

The Model 1 also had support for the Sega VR headset. It was used for only one known Model 1 game, Dennou Senki Net Merc. It is unknown whether Model 1 hardware was used for the VR-1.

Technical specifications

Technical specifications for Sega Model 1 hardware:[1]

  • Board composition: Main Board, Video Board, Memory Board, I/O Board, Communication Board, Sound Board, Motor Board, Audio Mix Board, Amp Board
    • Board revisions: CPU Board 837‑8886171‑6298C (40 MHz), Video PCB 837‑7894 (36 MHz), Memory Board 837‑7893, I/O PCB 837‑8950‑01 (32 MHz), Motor PCB SJ25‑0155‑01 (8 MHz), Communication Board 837‑8842, Sound Board 837‑8679 (20 MHz), Audio Mix PCB 839‑0542, Amp PCB 838‑10018
  • Main CPU: NEC V60 @ 16 MHz[8][9]
  • Additional CPU: 3× Zilog Z80 @ 4 MHz (8‑bit & 16‑bit instructions @ 1.74 MIPS)
    • CPU for I/O Board, Comm Board and Motor Board
  • DMA controllers: Fujitsu MB89237A DMAC, Fujitsu MB89374 Data Link Controller[10][11]

Sound

Graphics

Graphical capabilities of the Sega Model 1:[12]

Memory

  • Memory: Up to 39,166 KB (7008 KB main, 23,646 KB video, 8512 KB audio)
  • System RAM: 2776 KB (1896 KB high‑speed SRAM)
    • Main RAM: 480 KB (at least 156 KB SRAM)
      • Main Board: 324 KB (320 KB main, 4 KB comm)
      • Comm Board: 12 KB SRAM (8 KB SRAM, 4 KB Dual‑Port SRAM)[27][28]
      • Other boards: 144 KB SRAM (128 KB Memory Board, 8 KB I/O Board, 8 KB Motor Board)
    • VRAM: 2232 KB (at least 1464 KB SRAM)
      • Main Board: 768 KB (128 KB display lists, 576 KB tiles, 64 KB color)
      • Video Board: 1464 KB SRAM (1024 KB framebuffers)
    • Audio RAM: 64 KB (16 KB SRAM)
  • Internal DSP cache: 30 KB (6 KB per DSP)[14]
  • System ROM: 1 MB EPROM (768 KB Memory Board, 64 KB I/O Board, 64 KB Motor Board, 128 KB Comm Board)
  • Game ROM: Up to 35,336 KB (5504 KB main EPROM/MROM, 21,384 KB video MROM,[29] 8.25 MB audio MROM)[30]

Bandwidth

  • System RAM bandwidth: 664.224 MB/s
    • Main RAM: 76 MB/s
      • V60: 64 MB/s (32‑bit, 16 MHz)[31]
      • Z80: 12 MB/s (3× 8‑bit, 4 MHz)[32][33][28]
    • VRAM: 568.223776 MB/s
      • DSP: 320 MB/s (5× 32‑bit, 16 MHz)[31]
      • Video Board: 248.223776 MB/s (112-bit)
        • 315‑5422 & 315‑5292: 30.769232 MB/s (32‑bit, 7.692308 MHz, tilemaps)[34]
        • 315‑5423: 72 MB/s (16‑bit, 36 MHz)[31]
        • 315‑5424 & 315‑5425: 145.454544 MB/s (64‑bit, 18.181818 MHz, framebuffers)[35]
    • Audio RAM: 20 MB/s (16‑bit, 10 MHz)[32]
  • Internal processor bandwidth: 384 MB/s
    • V60: 64 MB/s (32‑bit, 16 MHz)
    • DSP cache: 320 MB/s (5× 32‑bit, 16 MHz)
  • System ROM bandwidth: 64 MB/s (32‑bit, 16 MHz)[36]
  • Game ROM bandwidth: 211 MB/s (3× 32‑bit)
    • EPROM: 64 MB/s (32‑bit, 16 MHz)[36]
    • MROM: 147 MB/s (2× 32‑bit, 20 MHz & 16.666667 MHz, 50/60 ns)[37][38]

List of games

Magazine articles

Main article: Sega Model 1/Magazine articles.

Photo gallery

  • Unit

  • Amplifier PCB

  • Communication PCB

  • CPU

  • Input/Output PCB

  • Sound PCB

  • Video PCB

Notes

  1. ↑ [5 instructions per cycle[15] 5 instructions per cycle[15]]
  2. ↑ MAC (multiply–accumulate) operation (multiply and add) per cycle[15]
  3. ↑ [1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)[15] 1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)[15]]
  4. ↑ [1024 KB, 512 KB per framebuffer, 2 bytes per pixel 1024 KB, 512 KB per framebuffer, 2 bytes per pixel]
  5. ↑ [144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color 144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color]
  6. ↑ [44 cycles (20 MAC operations, 2 divides) per vertex[12] 44 cycles (20 MAC operations, 2 divides) per vertex[12]]
  7. ↑ [4 vertices per quad polygon 4 vertices per quad polygon]
  8. ↑ [194 cycles (89 MAC operations, 8 divides) per quad polygon[12] 194 cycles (89 MAC operations, 8 divides) per quad polygon[12]]
  9. ↑ [206 cycles (95 MAC operations, 8 divides) per quad polygon[12] 206 cycles (95 MAC operations, 8 divides) per quad polygon[12]]
  10. ↑ [230 cycles (107 MAC operations, 8 divides) per quad polygon[19][20] 230 cycles (107 MAC operations, 8 divides) per quad polygon[19][20]]
  11. ↑ [388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),[22][23] 496 cycles per 32-pixel polygon (3 cycles per pixel) 388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),[22][23] 496 cycles per 32-pixel polygon (3 cycles per pixel)]
  12. ↑ [572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
    • Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,[24] 2 cycles per pixel)[25]
    • Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
    • Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)[26] 572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
    • Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,[24] 2 cycles per pixel)[25]
    • Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
    • Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)[26]]
  13. ↑ [628 cycles per 32-texel polygon
    • Gouraud shading: 388 cycles per 32-pixel polygon
    • Texture mapping: 240 cycles per 32-texel polygon 628 cycles per 32-texel polygon
    • Gouraud shading: 388 cycles per 32-pixel polygon
    • Texture mapping: 240 cycles per 32-texel polygon]

References

  1. ↑ 1.0 1.1 Sega Model 1 Hardware Overview (MAME)
  2. ↑ File:MeanMachinesSega26UK.pdf, page 18
  3. ↑ 3.0 3.1 http://www.thg.ru/smoke/19991022/print.html
  4. ↑ http://www.1up.com/features/disappearance-suzuki-part-1
  5. ↑ File:MeanMachinesSega19UK.pdf, page 51
  6. ↑ Yu Suzuki Interview, Strana Igr, November 2013
  7. ↑ 7.0 7.1 7.2 TGP (MAME)
  8. ↑ File:Overview of 32-bit V-Series Microprocessor.pdf
  9. ↑ File:UPD70616ProgrammersReferenceManual.pdf
  10. ↑ File:MB89396 datasheet.pdf
  11. ↑ File:MB89374 datasheet.pdf
  12. ↑ 12.0 12.1 12.2 12.3 Sega Model 1 Video Hardware (MAME)
  13. ↑ Sega Model 1 ROM Dump
  14. ↑ 14.0 14.1 File:MB86232 datasheet.pdf
  15. ↑ 15.0 15.1 15.2 File:MB86232 datasheet.pdf, page 32
  16. ↑ MODEL1 (アーケードゲーム基板@ ウィキ)
  17. ↑ Sega 16‑Bit Common Hardware, MAME
  18. ↑ Sega System 24 Hardware Notes (2013-06-16)
  19. ↑ Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)
  20. ↑ Design of Digital Systems and Devices (pages 95-97)
  21. ↑ File:GameOn US 06.pdf, page 11
  22. ↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
  23. ↑ File:32XUSHardwareManual.pdf, page 76
  24. ↑ Algorithms for Parallel Polygon Rendering (pages 33-36)
  25. ↑ Algorithms for Parallel Polygon Rendering (page 35)
  26. ↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)
  27. ↑ File:MB8421 datasheet.pdf
  28. ↑ 28.0 28.1 File:MB8431 datasheet.pdf
  29. ↑ http://mamedb.com/game/vformula
  30. ↑ http://mamedb.com/game/vf
  31. ↑ 31.0 31.1 31.2 File:M5M5178AP datasheet.pdf
  32. ↑ 32.0 32.1 File:MB8464A datasheet.pdf
  33. ↑ MB8432 Datasheet, Fujitsu
  34. ↑ File:HM658128A datasheet.pdf
  35. ↑ File:HM65256B datasheet.pdf
  36. ↑ 36.0 36.1 File:HN27C1024 datasheet.pdf
  37. ↑ File:MB8316200B datasheet.pdf
  38. ↑ File:MB834000 datasheet.pdf


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