Difference between revisions of "Sega Model 1"

Revision as of 13:57, 25 September 2020

Sega Model 1

Manufacturer: Sega

Release	Date	RRP	Code
JP	1992-08	¥?	837-8886171^[1]
UK	1992	£6,000^[2]	837-8886171
World	1992	?	837-8886171

The Sega Model 1 is an arcade system board that was released by Sega in 1992. It is the successor to the Sega System 32 (released in 1990). While earlier Sega hardware was capable of handling 3D polygons (such as the Mega Drive, released in 1988), the Model 1 was Sega's first hardware specifically designed for 3D polygon graphics.

Originally, the Model 1 was simply known as the CG Board, but was retroactively given the Model 1 name after work on the Model 2 began. The Model 1 was succeeded by the Sega Model 2 (released in 1993). Both the Model 1 and Model 2 were eventually succeeded by the Sega Model 3.

Hardware

The Model 1 board took three years to develop^[3], with Yu Suzuki's Sega AM2 team involved in its development from the drawing board.^[4] It was intended to compete with Namco's System 21; Namco was then the market leader in polygonal 3D video games, with titles such as Galaxian³ and Starblade.^[5] The Model 1 was eventually released in 1992, debuting with Virtua Racing. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform.

“	Dedicated 3D processors didn’t exist yet, and so I had to manually write a 3D graphics engine that would compress and process things faster. Just using assembly language. Now, of course, everyone writes in C++, but back then there was no other choice than machine code, otherwise we wouldn't be able to make everything fast enough.	„
— Yu Suzuki ^[6]

Unlike the Model 2, Lockheed Martin was not involved with the development of the Model 1, but it was developed internally at Sega, before Lockheed Martin became involved with the development of the Sega Model 2, according to former Lockheed Martin employee, Real3D's Jon Lenyo, in 1998.^[7]

Like the Model 2, Fujitsu was involved with the development of the Model 1. They provided the DSP coprocesors, which were modified by Sega with custom microcode for hardware T&L capabilities;^[8] hardware T&L would not appear on consumer home systems for many years. Fujitsu also provided several other components, including the tilemap generator chip, the DMA controllers, and several memory chips.

The Model 1 also had support for the Sega VR headset. It was used for only one known Model 1 game, Dennou Senki Net Merc. It is unknown whether Model 1 hardware was used for the VR-1.

The hardware was designed to cope with 180,000 polygons per second^[3].

Technical specifications

Technical specifications for Sega Model 1 hardware:^[1]

Board composition: Main Board, Video Board, Memory Board, I/O Board, Communication Board, Sound Board, Motor Board, Audio Mix Board, Amp Board

Board revisions: CPU Board 837‑8886171‑6298C (40 MHz), Video PCB 837‑7894 (36 MHz), Memory Board 837‑7893, I/O PCB 837‑8950‑01 (32 MHz), Motor PCB SJ25‑0155‑01 (8 MHz), Communication Board 837‑8842, Sound Board 837‑8679 (20 MHz), Audio Mix PCB 839‑0542, Amp PCB 838‑10018

Main CPU: NEC V60 @ 16 MHz^[9]^[10]

Fixed‑point arithmetic: 32‑bit RISC instructions, 3.5 MIPS
Floating‑point unit: 32‑bit & 64‑bit operations, 16 MFLOPS
Bus width: 32‑bit

Additional CPU: 3× Zilog Z80 @ 4 MHz (8‑bit & 16‑bit instructions @ 1.74 MIPS)

CPU for I/O Board, Comm Board and Motor Board

DMA controllers: Fujitsu MB89237A DMAC, Fujitsu MB89374 Data Link Controller^[11]^[12]

Sound

Sound CPU: Toshiba TMP68000N‑10 (68000) @ 12 MHz
Sound chips: 2× Sega 315‑5560 Custom MultiPCM

Audio capabilities: 28 PCM channels per chip (one for music, one for sound effects), 56 PCM channels total

Sound timer: Yamaha YM3834 @ 8 MHz

Graphics

Graphical capabilities of the Sega Model 1:^[13]

GPU: 5× Fujitsu TGP MB86233 DSP, Sega 837‑7894 171‑6080D Video PCB
GPU Geometrizer coprocessors: 5× Fujitsu TGP MB86233 DSP @ 16 MHz^[14]^[15]

Coprocessor abilities: Floating decimal point operation function, axis rotation operation function, 3D matrix operation function, ALU, DMA controller, T&L (transform, clipping, lighting)^[8]
Instruction set: 32‑bit instructions, 400 MIPS (80 MIPS each)^{[n 1]}
Fixed-point arithmetic: 160 MIPS (32 MIPS each)^{[n 2]}
Floating-point units: 80 MFLOPS (16 MFLOPS each)^{[n 3]}
Bus width: 160‑bit (32‑bit each)
Notes: DSP coprocessors located on Main Board. DSP are modified by Sega with custom microcode for coprocessor and T&L capabilities.^[8]

GPU Rasterizer Video Board: Sega 837‑7894 171‑6080D Video PCB @ 36 MHz,^[17] custom programmable logic devices programmed by Sega

315‑5292: Fujitsu LSI (QFP160), Sega System 24 tilemap generator,^[18]^[19] 2D tiled backgrounds
Sega 315‑5422A: Ricoh 5GU040-010 (QFP160)
Sega 315‑5423: Hitachi HG62E130R37F (QFP168)
Sega 315‑5424A: Hitachi HG62E130R36F (QFP168)
Sega 315‑5425: Hitachi HG62F58R12FL (QFP168)
3x Sega 315-5486: Lattice GAL16V8B25LP (DIP20), RGB output control

Display resolution: 496×384 pixels, 24 kHz H‑Sync, progressive scan (non‑interlaced)

Overscan resolution: 656×496 pixels
Polygon framebuffer: 512×512, double buffering, 16-bit color^{[n 4]}

Color depth: 65,536 (16‑bit color) to 16,777,216 (16‑bit color, 256 luminance levels)

Framebuffer color depth: 65,536 (16‑bit color)

Graphical capabilities: Lighting, shading, flat shading, diffuse reflection, specular reflection, specular lighting, 2 layers of background scrolling, alpha blending, alpha channel
Rendering fillrate: 68 MPixels/s

Polygon fillrate: 36 MPixels/s^{[n 5]}
Tilemap fillrate: 32 MPixels/s

Geometry calculations: 80 MFLOPS

Geometry transformations: 1.8 million vertices/sec,^{[n 6]} 450,000 polygons/sec^{[n 7]}
Lighting calculations: 410,000 polygons/sec (flat),^{[n 8]} 380,000 polygons/sec (specular),^{[n 9]} 340,000 polygons/sec (Gouraud)^{[n 10]}

Hardware rendering: 36 MPixels/s, lighting, flat shading

410,000 polygons/sec: 80-pixel polygons
380,000 polygons/sec: Specular, 90-pixel polygons
180,000 polygons/sec:^[22] Specular, all hardware effects, 200-pixel polygons

Software rendering: Lighting

160,000 polygons/sec: Gouraud shading, 32-pixel polygons^{[n 11]}
130,000 polygons/sec: Texture mapping, 32-texel polygons^{[n 12]}
120,000 polygons/sec: Texture mapping, Gouraud shading, 32-texel polygons^{[n 13]}

Hardware support: Sega VR

Memory

Memory: Up to 39,166 KB (7008 KB main, 23,646 KB video, 8512 KB audio)
System RAM: 2776 KB (1896 KB high‑speed SRAM)

Main RAM: 480 KB (at least 156 KB SRAM)

Main Board: 324 KB (320 KB main, 4 KB comm)
Comm Board: 12 KB SRAM (8 KB SRAM, 4 KB Dual‑Port SRAM)^[28]^[29]
Other boards: 144 KB SRAM (128 KB Memory Board, 8 KB I/O Board, 8 KB Motor Board)

VRAM: 2232 KB (at least 1464 KB SRAM)

Main Board: 768 KB (128 KB display lists, 576 KB tiles, 64 KB color)
Video Board: 1464 KB SRAM (1024 KB framebuffers)

Audio RAM: 64 KB (16 KB SRAM)

Internal DSP cache: 30 KB (6 KB per DSP)^[15]
System ROM: 1 MB EPROM (768 KB Memory Board, 64 KB I/O Board, 64 KB Motor Board, 128 KB Comm Board)
Game ROM: Up to 35,336 KB (5504 KB main EPROM/MROM, 21,384 KB video MROM,^[30] 8.25 MB audio MROM)^[31]

Bandwidth

System RAM bandwidth: 664.224 MB/s

Main RAM: 76 MB/s

V60: 64 MB/s (32‑bit, 16 MHz)^[32]
Z80: 12 MB/s (3× 8‑bit, 4 MHz)^[33]^[34]^[29]

VRAM: 568.223776 MB/s

DSP: 320 MB/s (5× 32‑bit, 16 MHz)^[32]
Video Board: 248.223776 MB/s (112-bit)

315‑5422 & 315‑5292: 30.769232 MB/s (32‑bit, 7.692308 MHz, tilemaps)^[35]
315‑5423: 72 MB/s (16‑bit, 36 MHz)^[32]
315‑5424 & 315‑5425: 145.454544 MB/s (64‑bit, 18.181818 MHz, framebuffers)^[36]

Audio RAM: 20 MB/s (16‑bit, 10 MHz)^[33]

Internal processor bandwidth: 384 MB/s

V60: 64 MB/s (32‑bit, 16 MHz)
DSP cache: 320 MB/s (5× 32‑bit, 16 MHz)

System ROM bandwidth: 64 MB/s (32‑bit, 16 MHz)^[37]
Game ROM bandwidth: 211 MB/s (3× 32‑bit)

EPROM: 64 MB/s (32‑bit, 16 MHz)^[37]
MROM: 147 MB/s (2× 32‑bit, 20 MHz & 16.666667 MHz, 50/60 ns)^[38]^[39]

List of games

Virtua Racing (1992)
Virtua Formula (1993)
Virtua Fighter (1993)
Star Wars Arcade (1994)
Wing War (1994)
Sega Net Merc (1995)
Dennou Senki Net Merc (1995)

Magazine articles

Main article: Sega Model 1/Magazine articles.

Photo gallery

Unit
Amplifier PCB
Communication PCB
CPU
Input/Output PCB
Sound PCB
Video PCB

Notes

↑ [5 instructions per cycle^[16] 5 instructions per cycle^[16]]
↑ MAC (multiply–accumulate) operation (multiply and add) per cycle^[16]
↑ [1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)^[16] 1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)^[16]]
↑ [1024 KB, 512 KB per framebuffer, 2 bytes per pixel 1024 KB, 512 KB per framebuffer, 2 bytes per pixel]
↑ [144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color 144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color]
↑ [44 cycles (20 MAC operations, 2 divides) per vertex^[13] 44 cycles (20 MAC operations, 2 divides) per vertex^[13]]
↑ [4 vertices per quad polygon 4 vertices per quad polygon]
↑ [194 cycles (89 MAC operations, 8 divides) per quad polygon^[13] 194 cycles (89 MAC operations, 8 divides) per quad polygon^[13]]
↑ [206 cycles (95 MAC operations, 8 divides) per quad polygon^[13] 206 cycles (95 MAC operations, 8 divides) per quad polygon^[13]]
↑ [230 cycles (107 MAC operations, 8 divides) per quad polygon^[20]^[21] 230 cycles (107 MAC operations, 8 divides) per quad polygon^[20]^[21]]
↑ [388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[23]^[24] 496 cycles per 32-pixel polygon (3 cycles per pixel) 388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[23]^[24] 496 cycles per 32-pixel polygon (3 cycles per pixel)]
↑
[572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
- Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]
- Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
- Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27] 572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
- Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]
- Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
- Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27]]
↑
[628 cycles per 32-texel polygon
- Gouraud shading: 388 cycles per 32-pixel polygon
- Texture mapping: 240 cycles per 32-texel polygon 628 cycles per 32-texel polygon
- Gouraud shading: 388 cycles per 32-pixel polygon
- Texture mapping: 240 cycles per 32-texel polygon]

References

Sega arcade boards
Originating in arcades
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 VIC Dual G80 Zaxxon VCO Object System 1 LaserDisc Appoooh Hang-On System 2 System 16 OutRun Gigas X Board Y Board System 24 System 18 System 32 Model 1 Model 2 H1 Board Model 3
Console-based hardware
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SG-1000 System E System C Mega-Tech System Mega Play Sega Titan Video NAOMI Hikaru NAOMI 2 Atomiswave System SP Chihiro Triforce
PC-based hardware
05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Lindbergh Europa-R RingEdge RingWide RingEdge 2 Nu Nu 1.1 Nu 2 ALLS

[5_instructions_per_cycle.7F.27.22.60UNIQ--ref-00000029-QINU.60.22.27.7F-17] [5 instructions per cycle^[16] 5 instructions per cycle^[16]]

[.5B.5Bwikipedia:Multiply.E2.80.93accumulate_operation.7CMAC_.28multiply.E2.80.93accumulate.29_operation.5D.5D_.28multiply_and_add.29_per_cycle.7F.27.22.60UNIQ--ref-0000002D-QINU.60.22.27.7F-18] MAC (multiply–accumulate) operation (multiply and add) per cycle^[16]

[1_operation_per_cycle_.282_cycles_per_MAC_operation.2C_2_cycles_per_divide.29.7F.27.22.60UNIQ--ref-00000031-QINU.60.22.27.7F-19] [1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)^[16] 1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)^[16]]

[1024_KB.2C_512_KB_per_framebuffer.2C_2_bytes_per_pixel-23] [1024 KB, 512 KB per framebuffer, 2 bytes per pixel 1024 KB, 512 KB per framebuffer, 2 bytes per pixel]

[144_MB.2Fsec_framebuffer_bandwidth.2C_double-buffered.2C_16-bit_color-24] [144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color 144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color]

[44_cycles_.2820_MAC_operations.2C_2_divides.29_per_vertex.7F.27.22.60UNIQ--ref-00000039-QINU.60.22.27.7F-25] [44 cycles (20 MAC operations, 2 divides) per vertex^[13] 44 cycles (20 MAC operations, 2 divides) per vertex^[13]]

[4_vertices_per_quad_polygon-26] [4 vertices per quad polygon 4 vertices per quad polygon]

[194_cycles_.2889_MAC_operations.2C_8_divides.29_per_quad_polygon.7F.27.22.60UNIQ--ref-0000003C-QINU.60.22.27.7F-27] [194 cycles (89 MAC operations, 8 divides) per quad polygon^[13] 194 cycles (89 MAC operations, 8 divides) per quad polygon^[13]]

[206_cycles_.2895_MAC_operations.2C_8_divides.29_per_quad_polygon.7F.27.22.60UNIQ--ref-0000003E-QINU.60.22.27.7F-28] [206 cycles (95 MAC operations, 8 divides) per quad polygon^[13] 206 cycles (95 MAC operations, 8 divides) per quad polygon^[13]]

[230_cycles_.28107_MAC_operations.2C_8_divides.29_per_quad_polygon.7F.27.22.60UNIQ--ref-00000040-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000041-QINU.60.22.27.7F-31] [230 cycles (107 MAC operations, 8 divides) per quad polygon^[20]^[21] 230 cycles (107 MAC operations, 8 divides) per quad polygon^[20]^[21]]

[388_cycles_.3Csmall.3E.28309_geometry_cycles.2C_40_RAM_cycles.2C_39_raster_operations.29.3C.2Fsmall.3E_400_cycles_per_4-scanline_polygon_.283_operations.2Fscanline_per_polygon.29.2C.7F.27.22.60UNIQ--ref-00000046-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000049-QINU.60.22.27.7F_496_cycles_per_32-pixel_polygon_.283_cycles_per_pixel.29-35] [388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[23]^[24] 496 cycles per 32-pixel polygon (3 cycles per pixel) 388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),^[23]^[24] 496 cycles per 32-pixel polygon (3 cycles per pixel)]

[572_cycles_.28332_cycles_flat_shading.2C_240_cycles_texture_mapping.29_per_32-texel_polygon.0A.2AFlat_shading:_332_cycles_per_32-pixel_polygon_.28194_geometry_cycles.2C_40_RAM_cycles.2C_34_raster_operations.2C.7F.27.22.60UNIQ--ref-0000004B-QINU.60.22.27.7F_2_cycles_per_pixel.29.7F.27.22.60UNIQ--ref-0000004C-QINU.60.22.27.7F.0A.2ATexture_mapping:_128_cycles_per_32-texel_texture:_2_block_moves.2C_2_cycles_per_texel_.282_bytes_per_texel.29.0A.2ATexture_mapping:_112_divide_cycles_per_32-texel_polygon:_56_divides_per_32-texel_polygon.2C_24_vertex_divide_cycles_per_polygon_.2812_divides_per_polygon.29.2C_64_texel_divide_cycles_per_32-texel_polygon_.2832_divides.2C_1_divide_per_texel.29.7F.27.22.60UNIQ--ref-0000004D-QINU.60.22.27.7F-39] [572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]

Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)

Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27] 572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon

Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]

Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)

Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27]]

[13] Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]

[14] Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)

[15] Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27] 572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon

[16] Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,^[25] 2 cycles per pixel)^[26]

[17] Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)

[18] Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)^[27]]

[628_cycles_per_32-texel_polygon.0A.2AGouraud_shading:_388_cycles_per_32-pixel_polygon.0A.2ATexture_mapping:_240_cycles_per_32-texel_polygon-40] [628 cycles per 32-texel polygon
Gouraud shading: 388 cycles per 32-pixel polygon

Texture mapping: 240 cycles per 32-texel polygon 628 cycles per 32-texel polygon

Gouraud shading: 388 cycles per 32-pixel polygon

Texture mapping: 240 cycles per 32-texel polygon]

[20] Gouraud shading: 388 cycles per 32-pixel polygon

[21] Texture mapping: 240 cycles per 32-texel polygon 628 cycles per 32-texel polygon

[22] Gouraud shading: 388 cycles per 32-pixel polygon

[23] Texture mapping: 240 cycles per 32-texel polygon]

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fmodel1.cpp_Sega_Model_1_Hardware_Overview_.28MAME.29.5D-1] 1.0 ^1.1 Sega Model 1 Hardware Overview (MAME)

[:File:MeanMachinesSega26UK.pdf_p18-2] Mean Machines Sega, "December 1994" (UK; 1994-10-28), page 18

[:File:Edge_UK_009.pdf_p47-3] 3.0 ^3.1 Edge, "June 1994" (UK; 1994-04-28), page 47

[https:.2F.2Farchive.is.2FqJee4-4] ttp://www.1up.com/features/disappearance-suzuki-part-1?pager.offset=2 (archive.today)

[:File:MeanMachinesSega19UK.pdf_p51-5] Mean Machines Sega, "May 1994" (UK; 1994-03-xx), page 51

[.5Bhttp:.2F.2Fwww.shenmuedojo.net.2Fforum.2Fviewtopic.php.3Ft.3D46577_Yu_Suzuki_Interview.5D.2C_.27.27.5B.5Bwikipedia:Strana_Igr.7CStrana_Igr.5D.5D.27.27.2C_November_2013-6] Yu Suzuki Interview, Strana Igr, November 2013

[http:.2F.2Fwww.thg.ru.2Fsmoke.2F19991022.2Fprint.html-7] ttp://www.thg.ru/smoke/19991022/print.html

[.5Bhttp:.2F.2Fwiki.mamedev.org.2Findex.php.2FTGP:Index_TGP_.28MAME.29.5D-8] 8.0 ^8.1 ^8.2 TGP (MAME)

[:File:Overview_of_32-bit_V-Series_Microprocessor.pdf_p-9] File:Overview of 32-bit V-Series Microprocessor.pdf

[:File:UPD70616ProgrammersReferenceManual.pdf_p-10] File:UPD70616ProgrammersReferenceManual.pdf

[:File:MB89396_datasheet.pdf_p-11] File:MB89396 datasheet.pdf

[:File:MB89374_datasheet.pdf_p-12] File:MB89374 datasheet.pdf

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fvideo.2Fmodel1.cpp_Sega_Model_1_Video_Hardware_.28MAME.29.5D-13] 13.0 ^13.1 ^13.2 ^13.3 Sega Model 1 Video Hardware (MAME)

[.5Bhttp:.2F.2Fmembers.iinet.net.au.2F.7Elantra9jp1_nbn.2Fgurudumps.2Fm2status.2Findex.html_Sega_Model_1_ROM_Dump.5D-14] Sega Model 1 ROM Dump

[:File:MB86232_datasheet.pdf_p-15] 15.0 ^15.1 File:MB86232 datasheet.pdf

[:File:MB86232_datasheet.pdf_p32-16] 16.0 ^16.1 ^16.2 File:MB86232 datasheet.pdf, page 32

[.5Bhttps:.2F.2Fwww40.atwiki.jp.2Farcadegames.2Fpages.2F17.html_MODEL1_.28.E3.82.A2.E3.83.BC.E3.82.B1.E3.83.BC.E3.83.89.E3.82.B2.E3.83.BC.E3.83.A0.E5.9F.BA.E6.9D.BF.40_.E3.82.A6.E3.82.A3.E3.82.AD.29.5D-20] MODEL1 (アーケードゲーム基板@ ウィキ)

[.5Bhttps:.2F.2Fgithub.com.2Fbji.2Flibmame.2Fblob.2Fmaster.2Fold.2Fsrc.2Fmame.2Fvideo.2Fsegaic16.c_Sega_16.E2.80.91Bit_Common_Hardware.5D.2C_.5B.5BMAME.5D.5D-21] Sega 16‑Bit Common Hardware, MAME

[Sega_System_24_Hardware_Notes_.282013-06-16.29-22] Sega System 24 Hardware Notes (2013-06-16)

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fvideo.2Fmodel2.cpp_Sega_Model_2_Geometry_Engine_and_3D_Rasterizer_.28MAME.29.5D-29] Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA95_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28pages_95-97.29.5D-30] Design of Digital Systems and Devices (pages 95-97)

[:File:GameOn_US_06.pdf_p11-32] File:GameOn US 06.pdf, page 11

[.5Bhttp:.2F.2Fsirkan.iit.bme.hu.2F.7Eszirmay.2Fabbas.pdf.23page.3D53_Transformation_Of_Rendering_Algorithms_For_Hardware_Implementation_.28page_53.29.5D-33] Transformation Of Rendering Algorithms For Hardware Implementation (page 53)

[:File:32XUSHardwareManual.pdf_p76-34] File:32XUSHardwareManual.pdf, page 76

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DyiVRHrxFj2wC.26pg.3DPA33_.27.27Algorithms_for_Parallel_Polygon_Rendering.27.27_.28pages_33-36.29.5D-36] Algorithms for Parallel Polygon Rendering (pages 33-36)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DyiVRHrxFj2wC.26pg.3DPA35_.27.27Algorithms_for_Parallel_Polygon_Rendering.27.27_.28page_35.29.5D-37] Algorithms for Parallel Polygon Rendering (page 35)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DteMHqC2BnuYC.26pg.3DPA110_.27.27State_of_the_Art_in_Computer_Graphics:_Visualization_and_Modeling.27.27_.28page_110.29.5D-38] State of the Art in Computer Graphics: Visualization and Modeling (page 110)

[:File:MB8421_datasheet.pdf_p-41] File:MB8421 datasheet.pdf

[:File:MB8431_datasheet.pdf_p-42] 29.0 ^29.1 File:MB8431 datasheet.pdf

[.5Bhttp:.2F.2Fmamedb.blu-ferret.co.uk.2Fgame.2Fvformula_Virtua_Formula_.28MAME.29.5D-43] Virtua Formula (MAME)

[.5Bhttp:.2F.2Fmamedb.blu-ferret.co.uk.2Fgame.2Fvf.2F_Virtua_Fighter_.28MAME.29.5D-44] Virtua Fighter (MAME)

[:File:M5M5178AP_datasheet.pdf_p-45] 32.0 ^32.1 ^32.2 File:M5M5178AP datasheet.pdf

[:File:MB8464A_datasheet.pdf_p-46] 33.0 ^33.1 File:MB8464A datasheet.pdf

[.5Bhttp:.2F.2Fwww.alldatasheet.com.2Fdatasheet-pdf.2Fpdf.2F120631.2FFUJITSU.2FMB8432.html_MB8432_Datasheet.5D.2C_.5B.5BFujitsu.5D.5D-47] MB8432 Datasheet, Fujitsu

[:File:HM658128A_datasheet.pdf_p-48] File:HM658128A datasheet.pdf

[:File:HM65256B_datasheet.pdf_p-49] File:HM65256B datasheet.pdf

[:File:HN27C1024_datasheet.pdf_p-50] 37.0 ^37.1 File:HN27C1024 datasheet.pdf

[:File:MB8316200B_datasheet.pdf_p-51] File:MB8316200B datasheet.pdf

[:File:MB834000_datasheet.pdf_p-52] File:MB834000 datasheet.pdf

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@@ Line 2: / Line 2: @@
 | logos=
 | consoleimage=Model1 board.jpg
-| imgwidth=320
 | name=
 | maker=[[Sega]]
@@ Line 21: / Line 20: @@
 ==Hardware==
-The Model 1 board took three years to develop{{magref|edge|9|47}}, with [[Yu Suzuki]]'s [[Sega AM2]] team involved in its development from the drawing board.{{ref|[https://archive.is/qJee4 The Disappearance of Yu Suzuki: Part 1 (page 3)]}} It was intended to compete with [[Namco]]'s [[wikia:w:c:gaming:Namco System 21|System 21]]; Namco was then the market leader in polygonal 3D video games, with titles such as ''[[wikipedia:Galaxian 3|Galaxian³]]'' and ''[[Starblade]]''.{{magref|mms|19|51}} The Model 1 was eventually released in 1992, debuting with ''[[Virtua Racing]]''. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform.
+The Model 1 board took three years to develop{{magref|edge|9|47}}, with [[Yu Suzuki]]'s [[Sega AM2]] team involved in its development from the drawing board.{{ref|https://archive.is/qJee4|2=http://www.1up.com/features/disappearance-suzuki-part-1?pager.offset=2}} It was intended to compete with [[Namco]]'s [[wikia:w:c:gaming:Namco System 21|System 21]]; Namco was then the market leader in polygonal 3D video games, with titles such as ''[[wikipedia:Galaxian 3|Galaxian³]]'' and ''[[Starblade]]''.{{magref|mms|19|51}} The Model 1 was eventually released in 1992, debuting with ''[[Virtua Racing]]''. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform.
 {{quoteRight|Dedicated 3D processors didn’t exist yet, and so I had to manually write a 3D graphics engine that would compress and process things faster. Just using assembly language. Now, of course, everyone writes in C++, but back then there was no other choice than machine code, otherwise we wouldn't be able to make everything fast enough.
 |[[Yu Suzuki]]