Difference between revisions of "Sega Model 1"
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| name= | | name= | ||
| maker=[[Sega]] | | maker=[[Sega]] | ||
| − | | releases={{ | + | | processor=[[NEC]] [[wikipedia:NEC V60|V60]] |
| − | | | + | | releases={{releasesArcade |
| − | | | + | | system_date_jp=1992-08 |
| + | | system_code_jp=837-8886171{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/model1.cpp Sega Model 1 Hardware Overview (MAME)]}} | ||
| + | | system_date_uk=1992 | ||
| + | | system_rrp_uk=6,000{{magref|mms|26|18}} | ||
| + | | system_code_uk=837-8886171 | ||
| + | | system_date_world=1992 | ||
| + | | system_code_world=837-8886171 | ||
}} | }} | ||
}} | }} | ||
| − | The '''Sega Model 1''' is an arcade system board released by Sega in 1992. It is the successor to the [[Sega System 32]] | + | The '''Sega Model 1''' (モデル1) is an [[arcade]] system board that was released by [[Sega]] in 1992. It is the successor to the [[Sega System 32]] (released in 1990). While earlier Sega hardware was capable of handling 3D polygons (such as the [[Mega Drive]], released in 1988), the Model 1 was Sega's first hardware specifically designed for 3D polygon graphics. |
| − | Originally, the Model 1 was simply known as the '''CG Board''', but was retroactively given the Model 1 name after work on the Model 2 began. | + | Originally, the Model 1 was simply known as the '''CG Board''' (CGボード), but was retroactively given the Model 1 name after work on the Model 2 began. The Model 1 was succeeded by the [[Sega Model 2]] (released in 1993). Both the Model 1 and Model 2 were eventually succeeded by the [[Sega Model 3]]. |
==Hardware== | ==Hardware== | ||
| − | + | The Model 1 board took three years to develop{{magref|edge|9|47}}, with [[Yu Suzuki]]'s [[Sega AM2]] team involved in its development from the drawing board.{{ref|https://archive.is/qJee4|2=http://www.1up.com/features/disappearance-suzuki-part-1?pager.offset=2}} It was intended to compete with [[Namco]]'s [[wikia:w:c:gaming:Namco System 21|System 21]]; Namco was then the market leader in polygonal 3D video games, with titles such as ''[[wikipedia:Galaxian 3|Galaxian³]]'' and ''[[Starblade]]''.{{magref|mms|19|51}} The Model 1 was eventually released in 1992, debuting with ''[[Virtua Racing]]''. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform. | |
| + | {{quoteRight|Dedicated 3D processors didn’t exist yet, and so I had to manually write a 3D graphics engine that would compress and process things faster. Just using assembly language. Now, of course, everyone writes in C++, but back then there was no other choice than machine code, otherwise we wouldn't be able to make everything fast enough. | ||
| + | |[[Yu Suzuki]] | ||
| + | |ref={{ref|1=[http://www.shenmuedojo.net/forum/viewtopic.php?t=46577 Yu Suzuki Interview], ''[[wikipedia:Strana Igr|Strana Igr]]'', November 2013}} | ||
| + | }} | ||
| + | Unlike the Model 2, [[Lockheed Martin]] was not involved with the development of the Model 1, but it was developed internally at Sega, before Lockheed Martin became involved with the development of the [[Sega Model 2]], according to former Lockheed Martin employee, [[Lockheed Martin|Real3D]]'s Jon Lenyo, in 1998.{{ref|http://www.thg.ru/smoke/19991022/print.html}} | ||
| + | |||
| + | Like the Model 2, [[Fujitsu]] was involved with the development of the Model 1. They provided the DSP coprocesors, which were modified by Sega with custom microcode for hardware [[wikipedia:T&L|T&L]] capabilities;{{ref|[http://wiki.mamedev.org/index.php/TGP:Index TGP (MAME)]}} hardware T&L would not appear on consumer home systems for many years. Fujitsu also provided several other components, including the tilemap generator chip, the DMA controllers, and several memory chips. | ||
| + | |||
| + | The Model 1 also had support for the [[Mega Visor Display]] headset. It was used for only one known Model 1 game, ''[[Dennou Senki Net Merc]]''. It is unknown whether Model 1 hardware was used for the [[VR-1]]. | ||
| + | |||
| + | The hardware was designed to cope with 180,000 polygons per second{{magref|edge|9|47}}. | ||
| + | |||
| + | ==Technical specifications== | ||
| + | Technical specifications for Sega Model 1 hardware:{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/model1.cpp Sega Model 1 Hardware Overview (MAME)]}} | ||
| − | + | {{multicol| | |
| + | * Board composition: Main Board, Video Board, Memory Board, I/O Board, Communication Board, Sound Board, Motor Board, Audio Mix Board, Amp Board | ||
| + | :* Board revisions: CPU Board 837‑8886171‑6298C (40 MHz), Video PCB 837‑7894 (36 MHz), Memory Board 837‑7893, I/O PCB 837‑8950‑01 (32 MHz), Motor PCB SJ25‑0155‑01 (8 MHz), Communication Board 837‑8842, Sound Board 837‑8679 (20 MHz), Audio Mix PCB 839‑0542, Amp PCB 838‑10018 | ||
| + | * Main [[wikipedia:Central processing unit|CPU]]: [[NEC]] [[V60]] @ 16 MHz{{fileref|Overview of 32-bit V-Series Microprocessor.pdf}}{{fileref|UPD70616ProgrammersReferenceManual.pdf}} | ||
| + | :* [[wikipedia:Fixed-point arithmetic|Fixed‑point arithmetic]]: 32‑bit [[wikipedia:Reduced instruction set computing|RISC]] [[wikipedia:Instruction set|instructions]], 3.5 [[wikipedia:Instructions per second|MIPS]] | ||
| + | :* [[wikipedia:Floating‑point unit|Floating‑point unit]]: [[wikipedia:Single-precision floating‑point format|32‑bit]] & [[wikipedia:Double-precision floating‑point format|64‑bit operations]], 16 MFLOPS | ||
| + | :* Bus width: 32‑bit | ||
| + | * Additional CPU: 3× [[Zilog Z80]] @ 4 MHz (8‑bit & 16‑bit instructions @ 1.74 MIPS) | ||
| + | :* CPU for I/O Board, Comm Board and Motor Board | ||
| + | * [[wikipedia:Direct memory access|DMA]] controllers: Fujitsu MB89237A DMAC, [[Fujitsu]] MB89374 Data Link Controller{{fileref|MB89396 datasheet.pdf}}{{fileref|MB89374 datasheet.pdf}} | ||
| + | }} | ||
| − | == | + | ===Sound=== |
| − | * | + | * Sound CPU: [[Toshiba]] TMP68000N‑10 ([[68000]]) @ 12 MHz |
| − | + | * Sound chips: 2× [[Yamaha YMW258-F|Sega 315‑5560 MultiPCM]] | |
| − | + | :* Audio capabilities: 28 [[Pulse-code modulation|PCM]] channels per chip (one for music, one for sound effects), 56 PCM channels total | |
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| − | * Sound chips: 2× Sega | ||
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* Sound timer: [[Yamaha]] YM3834 @ 8 MHz | * Sound timer: [[Yamaha]] YM3834 @ 8 MHz | ||
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| − | == | + | ===Graphics=== |
| − | + | Graphical capabilities of the Sega Model 1:{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/video/model1.cpp Sega Model 1 Video Hardware (MAME)]}} | |
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| − | == | + | {{multicol| |
| + | * GPU: 5× Fujitsu TGP MB86233 DSP, Sega 837‑7894 171‑6080D Video PCB | ||
| + | * GPU [[wikipedia:Geometry pipelines|Geometrizer]] [[wikipedia:Coprocessor|coprocessors]]: 5× [[Fujitsu]] TGP MB86233 [[wikipedia:Digital signal processor|DSP]] @ 16 MHz{{ref|[http://members.iinet.net.au/~lantra9jp1_nbn/gurudumps/m2status/index.html Sega Model 1 ROM Dump]}}{{fileref|MB86232 datasheet.pdf}} | ||
| + | :* Coprocessor abilities: [[wikipedia:Decimal floating point|Floating decimal point]] operation function, axis rotation operation function, 3D [[wikipedia:Matrix (mathematics)|matrix operation]] function, [[wikipedia:Arithmetic logic unit|ALU]], DMA controller, T&L (transform, clipping, lighting){{ref|[http://wiki.mamedev.org/index.php/TGP:Index TGP (MAME)]}} | ||
| + | :* Instruction set: 32‑bit instructions, 400 [[wikipedia:Million instructions per second|MIPS]] (80 MIPS each){{ref|5 instructions per cycle{{fileref|MB86232 datasheet.pdf|page=32}}|group=n}} | ||
| + | :* [[wikipedia:Fixed-point arithmetic|Fixed-point arithmetic]]: 160 MIPS (32 MIPS each){{ref|[[wikipedia:Multiply–accumulate operation|MAC (multiply–accumulate) operation]] (multiply and add) per cycle{{fileref|MB86232 datasheet.pdf|page=32}}|group=n}} | ||
| + | :* [[wikipedia:Floating point unit|Floating-point units]]: 80 MFLOPS (16 MFLOPS each){{ref|1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide){{fileref|MB86232 datasheet.pdf|page=32}}|group=n}} | ||
| + | :* Bus width: 160‑bit (32‑bit each) | ||
| + | :* Notes: DSP coprocessors located on Main Board. DSP are modified by Sega with custom microcode for coprocessor and T&L capabilities.{{ref|[http://wiki.mamedev.org/index.php/TGP:Index TGP (MAME)]}} | ||
| + | * GPU [[wikipedia:Rasterisation|Rasterizer]] Video Board: Sega 837‑7894 171‑6080D Video PCB @ 36 MHz,{{ref|[https://www40.atwiki.jp/arcadegames/pages/17.html MODEL1 (アーケードゲーム基板@ ウィキ)]}} custom [[wikipedia:Programmable logic device|programmable logic devices]] programmed by Sega | ||
| + | :* 315‑5292: [[Fujitsu]] [[wikipedia:Large Scale Integration|LSI]] ([[wikipedia:Quad Flat Package|QFP160]]), [[Sega System 24]] [[wikipedia:Tile-based video game|tilemap]] generator,{{ref|[https://github.com/bji/libmame/blob/master/old/src/mame/video/segaic16.c Sega 16‑Bit Common Hardware], [[MAME]]}}{{intref|Sega System 24 Hardware Notes (2013-06-16)}} 2D [[Sprite|tiled]] backgrounds | ||
| + | :* Sega 315‑5422A: [[Ricoh]] 5GU040-010 (QFP160) | ||
| + | :* Sega 315‑5423: [[Hitachi]] HG62E130R37F (QFP168) | ||
| + | :* Sega 315‑5424A: Hitachi HG62E130R36F (QFP168) | ||
| + | :* Sega 315‑5425: Hitachi HG62F58R12FL (QFP168) | ||
| + | :* 3x Sega 315-5486: [[wikipedia:Lattice Semiconductor|Lattice]] [[wikipedia:Gate Array Logic|GAL16V8B25LP]] ([[wikipedia:Dual in-line package|DIP20]]), RGB output control | ||
| + | * Display [[resolution]]: 496×384 [[pixel]]s, 24 kHz [[wikipedia:Horizontal scan rate|H‑Sync]], [[wikipedia:Progressive scan|progressive scan]] (non‑interlaced) | ||
| + | :* Overscan resolution: 656×496 pixels | ||
| + | :* Polygon framebuffer: 512×512, double buffering, 16-bit color{{ref|1024 KB, 512 KB per framebuffer, 2 bytes per pixel|group=n}} | ||
| + | * [[Palette|Color depth]]: 65,536 (16‑bit color) to 16,777,216 (16‑bit color, 256 luminance levels) | ||
| + | :* Framebuffer color depth: 65,536 (16‑bit color) | ||
| + | * Graphical capabilities: [[wikipedia:Computer graphics lighting|Lighting]], [[wikipedia:Shading|shading]], [[wikipedia:flat shading|flat shading]], [[wikipedia:Diffuse reflection|diffuse reflection]], [[wikipedia:Specular reflection|specular reflection]], [[wikipedia:Specular highlight|specular lighting]], 2 layers of background [[wikipedia:Scrolling|scrolling]], [[wikipedia:Alpha blending|alpha blending]], [[wikipedia:Alpha compositing|alpha channel]] | ||
| + | * Rendering [[fillrate]]: 68 [[Pixel|MPixels/s]] | ||
| + | :* Polygon fillrate: 36 MPixels/s{{ref|144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color|group=n}} | ||
| + | :* Tilemap fillrate: 32 MPixels/s | ||
| + | * Geometry calculations: 80 MFLOPS | ||
| + | :* Geometry transformations: 1.8 million vertices/sec,{{ref|44 cycles (20 MAC operations, 2 divides) per vertex{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/video/model1.cpp Sega Model 1 Video Hardware (MAME)]}}|group=n}} 450,000 polygons/sec{{ref|4 vertices per quad polygon|group=n}} | ||
| + | :* [[wikipedia:Transform and lighting|Lighting calculations]]: 410,000 polygons/sec ([[wikipedia:Flat shading|flat]]),{{ref|194 cycles (89 MAC operations, 8 divides) per quad polygon{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/video/model1.cpp Sega Model 1 Video Hardware (MAME)]}}|group=n}} 380,000 polygons/sec ([[wikipedia:Specular highlight|specular]]),{{ref|206 cycles (95 MAC operations, 8 divides) per quad polygon{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/video/model1.cpp Sega Model 1 Video Hardware (MAME)]}}|group=n}} 340,000 polygons/sec ([[wikipedia:Gouraud shading|Gouraud]]){{ref|230 cycles (107 MAC operations, 8 divides) per quad polygon{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/video/model2.cpp Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)]}}{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA95 ''Design of Digital Systems and Devices'' (pages 95-97)]}}|group=n}} | ||
| + | * Hardware rendering: 36 MPixels/s, lighting, [[wikipedia:Flat shading|flat shading]] | ||
| + | :* 410,000 polygons/sec: 80-pixel polygons | ||
| + | :* 380,000 polygons/sec: Specular, 90-pixel polygons | ||
| + | :* 180,000 polygons/sec:{{fileref|GameOn US 06.pdf|page=11}} Specular, all hardware effects, 200-pixel polygons | ||
| + | * Software rendering: Lighting | ||
| + | :* 160,000 polygons/sec: [[wikipedia:Gouraud shading|Gouraud shading]], 32-pixel polygons{{ref|388 cycles <small>(309 geometry cycles, 40 RAM cycles, 39 raster operations)</small> 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),{{ref|1=[http://sirkan.iit.bme.hu/~szirmay/abbas.pdf#page=53 Transformation Of Rendering Algorithms For Hardware Implementation (page 53)]}}{{fileref|32XUSHardwareManual.pdf|page=76}} 496 cycles per 32-pixel polygon (3 cycles per pixel)|group=n}} | ||
| + | :* 130,000 polygons/sec: Texture mapping, 32-texel polygons{{ref|1=572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon | ||
| + | *Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,{{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA33 ''Algorithms for Parallel Polygon Rendering'' (pages 33-36)]}} 2 cycles per pixel){{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA35 ''Algorithms for Parallel Polygon Rendering'' (page 35)]}} | ||
| + | *Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel) | ||
| + | *Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel){{ref|1=[https://books.google.co.uk/books?id=teMHqC2BnuYC&pg=PA110 ''State of the Art in Computer Graphics: Visualization and Modeling'' (page 110)]}} | ||
| + | |group=n}} | ||
| + | :* 120,000 polygons/sec: Texture mapping, Gouraud shading, 32-texel polygons{{ref|1=628 cycles per 32-texel polygon | ||
| + | *Gouraud shading: 388 cycles per 32-pixel polygon | ||
| + | *Texture mapping: 240 cycles per 32-texel polygon | ||
| + | |group=n}} | ||
| + | * Hardware support: [[Sega VR]] | ||
| + | }} | ||
| + | |||
| + | ===Memory=== | ||
| + | {{multicol| | ||
| + | * Memory: Up to 39,166 [[Byte|KB]] (7008 KB main, 23,646 KB video, 8512 KB audio) | ||
| + | * System [[RAM]]: 2776 KB (1896 KB high‑speed [[SRAM]]) | ||
| + | :* Main RAM: 480 KB (at least 156 KB SRAM) | ||
| + | ::* Main Board: 324 KB (320 KB main, 4 KB comm) | ||
| + | ::* Comm Board: 12 KB SRAM (8 KB SRAM, 4 KB [[wikipedia:Dual‑ported RAM|Dual‑Port]] SRAM){{fileref|MB8421 datasheet.pdf}}{{fileref|MB8431 datasheet.pdf}} | ||
| + | ::* Other boards: 144 KB [[SRAM]] (128 KB Memory Board, 8 KB I/O Board, 8 KB Motor Board) | ||
| + | :* [[VRAM]]: 2232 KB (at least 1464 KB SRAM) | ||
| + | ::* Main Board: 768 KB (128 KB [[wikipedia:Display list|display lists]], 576 KB [[wikipedia:Tiled rendering|tiles]], 64 KB color) | ||
| + | ::* Video Board: 1464 KB SRAM (1024 KB framebuffers) | ||
| + | :* Audio RAM: 64 KB (16 KB SRAM) | ||
| + | * Internal DSP [[wikipedia:Cache (computing)|cache]]: 30 KB (6 KB per DSP){{fileref|MB86232 datasheet.pdf}} | ||
| + | * System [[ROM]]: 1 [[Byte|MB]] [[EPROM]] (768 KB Memory Board, 64 KB I/O Board, 64 KB Motor Board, 128 KB Comm Board) | ||
| + | * Game ROM: Up to 35,336 KB (5504 KB main EPROM/[[wikipedia:Mask ROM|MROM]], 21,384 KB video MROM,{{ref|[http://mamedb.blu-ferret.co.uk/game/vformula Virtua Formula (MAME)]}} 8.25 MB audio MROM){{ref|[http://mamedb.blu-ferret.co.uk/game/vf/ Virtua Fighter (MAME)]}} | ||
| + | }} | ||
| + | |||
| + | ===Bandwidth=== | ||
| + | {{multicol| | ||
| + | * System RAM bandwidth: 664.224 MB/s | ||
| + | :* Main RAM: 76 MB/s | ||
| + | ::* V60: 64 MB/s <small>(32‑bit, 16 MHz)</small>{{fileref|M5M5178AP datasheet.pdf}} | ||
| + | ::* Z80: 12 MB/s <small>(3× 8‑bit, 4 MHz)</small>{{fileref|MB8464A datasheet.pdf}}{{ref|[http://www.alldatasheet.com/datasheet-pdf/pdf/120631/FUJITSU/MB8432.html MB8432 Datasheet], [[Fujitsu]]}}{{fileref|MB8431 datasheet.pdf}} | ||
| + | :* VRAM: 568.223776 MB/s | ||
| + | ::* DSP: 320 MB/s <small>(5× 32‑bit, 16 MHz)</small>{{fileref|M5M5178AP datasheet.pdf}} | ||
| + | ::* Video Board: 248.223776 MB/s (112-bit) | ||
| + | :::* 315‑5422 & 315‑5292: 30.769232 MB/s <small>(32‑bit, 7.692308 MHz, tilemaps)</small>{{fileref|HM658128A datasheet.pdf}} | ||
| + | :::* 315‑5423: 72 MB/s <small>(16‑bit, 36 MHz)</small>{{fileref|M5M5178AP datasheet.pdf}} | ||
| + | :::* 315‑5424 & 315‑5425: 145.454544 MB/s <small>(64‑bit, 18.181818 MHz, framebuffers)</small>{{fileref|HM65256B datasheet.pdf}} | ||
| + | :* Audio RAM: 20 MB/s <small>(16‑bit, 10 MHz)</small>{{fileref|MB8464A datasheet.pdf}} | ||
| + | * Internal processor bandwidth: 384 MB/s | ||
| + | :* V60: 64 MB/s <small>(32‑bit, 16 MHz)</small> | ||
| + | :* DSP cache: 320 MB/s <small>(5× 32‑bit, 16 MHz)</small> | ||
| + | * System ROM bandwidth: 64 MB/s <small>(32‑bit, 16 MHz)</small>{{fileref|HN27C1024 datasheet.pdf}} | ||
| + | * Game ROM bandwidth: 211 MB/s <small>(3× 32‑bit)</small> | ||
| + | :* EPROM: 64 MB/s <small>(32‑bit, 16 MHz)</small>{{fileref|HN27C1024 datasheet.pdf}} | ||
| + | :* MROM: 147 MB/s <small>(2× 32‑bit, 20 MHz & 16.666667 MHz, 50/60 [[wikipedia:Nanosecond|ns]])</small>{{fileref|MB8316200B datasheet.pdf}}{{fileref|MB834000 datasheet.pdf}} | ||
| + | }} | ||
| + | |||
| + | ==List of games== | ||
| + | {{BulletPointGameList|MOD1}} | ||
| + | |||
| + | ==Production credits== | ||
| + | {{creditstable| | ||
| + | *[[Toshiyuki Kaji]] | ||
| + | *'''Bug Fixing:''' [[Hiroshi Yagi]] | ||
| + | | source=Developer mentions{{ref|https://web.archive.org/web/20231110103013/https://game.watch.impress.co.jp/docs/news/758667.html}}{{ref|https://web.archive.org/web/20210205150032/https://www.4gamer.net/games/999/G999905/20210126043/}} | ||
| + | | console=Arcade | ||
| + | }} | ||
| + | |||
| + | ==Magazine articles== | ||
| + | {{mainArticle|{{PAGENAME}}/Magazine articles}} | ||
| + | |||
| + | ==Photo gallery== | ||
<gallery> | <gallery> | ||
| − | + | SegaModel1 SegaofJapan board lineup.jpg|Official [[Sega of Japan]] photograph of various Model 1 PCBs | |
| − | + | Model1 board.jpg|Unit | |
| − | + | Model1 amp.jpg|Amplifier PCB | |
| − | + | Model1 communication.jpg|Communication PCB | |
| − | + | Model1 cpu.jpg|CPU | |
| − | + | Model1 io.jpg|Input/Output PCB | |
| − | + | Model1 soundboard.jpg|Sound PCB | |
| + | Model1 videoboard.jpg|Video PCB | ||
</gallery> | </gallery> | ||
| + | |||
| + | ==Notes== | ||
| + | {{multicol| | ||
| + | <references group="n"/> | ||
| + | }} | ||
| + | |||
| + | ==References== | ||
| + | <references/> | ||
{{Sega Arcade Boards}} | {{Sega Arcade Boards}} | ||
[[Category:Sega Model series]] | [[Category:Sega Model series]] | ||
Latest revision as of 06:34, 10 November 2023
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The Sega Model 1 (モデル1) is an arcade system board that was released by Sega in 1992. It is the successor to the Sega System 32 (released in 1990). While earlier Sega hardware was capable of handling 3D polygons (such as the Mega Drive, released in 1988), the Model 1 was Sega's first hardware specifically designed for 3D polygon graphics.
Originally, the Model 1 was simply known as the CG Board (CGボード), but was retroactively given the Model 1 name after work on the Model 2 began. The Model 1 was succeeded by the Sega Model 2 (released in 1993). Both the Model 1 and Model 2 were eventually succeeded by the Sega Model 3.
Contents
Hardware
The Model 1 board took three years to develop[3], with Yu Suzuki's Sega AM2 team involved in its development from the drawing board.[4] It was intended to compete with Namco's System 21; Namco was then the market leader in polygonal 3D video games, with titles such as Galaxian³ and Starblade.[5] The Model 1 was eventually released in 1992, debuting with Virtua Racing. While it was a significant improvement over the System 21, the Model 1 hardware was expensive, and only a few games were developed for the platform.
| “ | Dedicated 3D processors didn’t exist yet, and so I had to manually write a 3D graphics engine that would compress and process things faster. Just using assembly language. Now, of course, everyone writes in C++, but back then there was no other choice than machine code, otherwise we wouldn't be able to make everything fast enough. | „ |
Unlike the Model 2, Lockheed Martin was not involved with the development of the Model 1, but it was developed internally at Sega, before Lockheed Martin became involved with the development of the Sega Model 2, according to former Lockheed Martin employee, Real3D's Jon Lenyo, in 1998.[7]
Like the Model 2, Fujitsu was involved with the development of the Model 1. They provided the DSP coprocesors, which were modified by Sega with custom microcode for hardware T&L capabilities;[8] hardware T&L would not appear on consumer home systems for many years. Fujitsu also provided several other components, including the tilemap generator chip, the DMA controllers, and several memory chips.
The Model 1 also had support for the Mega Visor Display headset. It was used for only one known Model 1 game, Dennou Senki Net Merc. It is unknown whether Model 1 hardware was used for the VR-1.
The hardware was designed to cope with 180,000 polygons per second[3].
Technical specifications
Technical specifications for Sega Model 1 hardware:[1]
- Board composition: Main Board, Video Board, Memory Board, I/O Board, Communication Board, Sound Board, Motor Board, Audio Mix Board, Amp Board
- Board revisions: CPU Board 837‑8886171‑6298C (40 MHz), Video PCB 837‑7894 (36 MHz), Memory Board 837‑7893, I/O PCB 837‑8950‑01 (32 MHz), Motor PCB SJ25‑0155‑01 (8 MHz), Communication Board 837‑8842, Sound Board 837‑8679 (20 MHz), Audio Mix PCB 839‑0542, Amp PCB 838‑10018
- Fixed‑point arithmetic: 32‑bit RISC instructions, 3.5 MIPS
- Floating‑point unit: 32‑bit & 64‑bit operations, 16 MFLOPS
- Bus width: 32‑bit
- Additional CPU: 3× Zilog Z80 @ 4 MHz (8‑bit & 16‑bit instructions @ 1.74 MIPS)
- CPU for I/O Board, Comm Board and Motor Board
Sound
- Sound CPU: Toshiba TMP68000N‑10 (68000) @ 12 MHz
- Sound chips: 2× Sega 315‑5560 MultiPCM
- Audio capabilities: 28 PCM channels per chip (one for music, one for sound effects), 56 PCM channels total
- Sound timer: Yamaha YM3834 @ 8 MHz
Graphics
Graphical capabilities of the Sega Model 1:[13]
- GPU: 5× Fujitsu TGP MB86233 DSP, Sega 837‑7894 171‑6080D Video PCB
- GPU Geometrizer coprocessors: 5× Fujitsu TGP MB86233 DSP @ 16 MHz[14][15]
- Coprocessor abilities: Floating decimal point operation function, axis rotation operation function, 3D matrix operation function, ALU, DMA controller, T&L (transform, clipping, lighting)[8]
- Instruction set: 32‑bit instructions, 400 MIPS (80 MIPS each)[n 1]
- Fixed-point arithmetic: 160 MIPS (32 MIPS each)[n 2]
- Floating-point units: 80 MFLOPS (16 MFLOPS each)[n 3]
- Bus width: 160‑bit (32‑bit each)
- Notes: DSP coprocessors located on Main Board. DSP are modified by Sega with custom microcode for coprocessor and T&L capabilities.[8]
- GPU Rasterizer Video Board: Sega 837‑7894 171‑6080D Video PCB @ 36 MHz,[17] custom programmable logic devices programmed by Sega
- 315‑5292: Fujitsu LSI (QFP160), Sega System 24 tilemap generator,[18][19] 2D tiled backgrounds
- Sega 315‑5422A: Ricoh 5GU040-010 (QFP160)
- Sega 315‑5423: Hitachi HG62E130R37F (QFP168)
- Sega 315‑5424A: Hitachi HG62E130R36F (QFP168)
- Sega 315‑5425: Hitachi HG62F58R12FL (QFP168)
- 3x Sega 315-5486: Lattice GAL16V8B25LP (DIP20), RGB output control
- Display resolution: 496×384 pixels, 24 kHz H‑Sync, progressive scan (non‑interlaced)
- Overscan resolution: 656×496 pixels
- Polygon framebuffer: 512×512, double buffering, 16-bit color[n 4]
- Color depth: 65,536 (16‑bit color) to 16,777,216 (16‑bit color, 256 luminance levels)
- Framebuffer color depth: 65,536 (16‑bit color)
- Graphical capabilities: Lighting, shading, flat shading, diffuse reflection, specular reflection, specular lighting, 2 layers of background scrolling, alpha blending, alpha channel
- Rendering fillrate: 68 MPixels/s
- Polygon fillrate: 36 MPixels/s[n 5]
- Tilemap fillrate: 32 MPixels/s
- Geometry calculations: 80 MFLOPS
- Hardware rendering: 36 MPixels/s, lighting, flat shading
- 410,000 polygons/sec: 80-pixel polygons
- 380,000 polygons/sec: Specular, 90-pixel polygons
- 180,000 polygons/sec:[22] Specular, all hardware effects, 200-pixel polygons
- Software rendering: Lighting
- 160,000 polygons/sec: Gouraud shading, 32-pixel polygons[n 11]
- 130,000 polygons/sec: Texture mapping, 32-texel polygons[n 12]
- 120,000 polygons/sec: Texture mapping, Gouraud shading, 32-texel polygons[n 13]
- Hardware support: Sega VR
Memory
- Memory: Up to 39,166 KB (7008 KB main, 23,646 KB video, 8512 KB audio)
- System RAM: 2776 KB (1896 KB high‑speed SRAM)
- Main RAM: 480 KB (at least 156 KB SRAM)
- VRAM: 2232 KB (at least 1464 KB SRAM)
- Main Board: 768 KB (128 KB display lists, 576 KB tiles, 64 KB color)
- Video Board: 1464 KB SRAM (1024 KB framebuffers)
- Audio RAM: 64 KB (16 KB SRAM)
Bandwidth
- System RAM bandwidth: 664.224 MB/s
- Main RAM: 76 MB/s
- VRAM: 568.223776 MB/s
- DSP: 320 MB/s (5× 32‑bit, 16 MHz)[32]
- Video Board: 248.223776 MB/s (112-bit)
- Audio RAM: 20 MB/s (16‑bit, 10 MHz)[33]
- Internal processor bandwidth: 384 MB/s
- V60: 64 MB/s (32‑bit, 16 MHz)
- DSP cache: 320 MB/s (5× 32‑bit, 16 MHz)
- System ROM bandwidth: 64 MB/s (32‑bit, 16 MHz)[37]
- Game ROM bandwidth: 211 MB/s (3× 32‑bit)
List of games
- Dennou Senki Net Merc (1995)
- Sega Net Merc (1995)
- Star Wars Arcade (1993)
- Virtua Fighter (1993)
- Virtua Formula (1993)
- Virtua Racing (1992)
- Wing War (1994)
Production credits
- Toshiyuki Kaji
- Bug Fixing: Hiroshi Yagi
Magazine articles
- Main article: Sega Model 1/Magazine articles.
Photo gallery
Official Sega of Japan photograph of various Model 1 PCBs
Unit
Amplifier PCB
Communication PCB
CPU
Input/Output PCB
Sound PCB
Video PCB
Notes
- ↑ [5 instructions per cycle[16] 5 instructions per cycle[16]]
- ↑ MAC (multiply–accumulate) operation (multiply and add) per cycle[16]
- ↑ [1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)[16] 1 operation per cycle (2 cycles per MAC operation, 2 cycles per divide)[16]]
- ↑ [1024 KB, 512 KB per framebuffer, 2 bytes per pixel 1024 KB, 512 KB per framebuffer, 2 bytes per pixel]
- ↑ [144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color 144 MB/sec framebuffer bandwidth, double-buffered, 16-bit color]
- ↑ [44 cycles (20 MAC operations, 2 divides) per vertex[13] 44 cycles (20 MAC operations, 2 divides) per vertex[13]]
- ↑ [4 vertices per quad polygon 4 vertices per quad polygon]
- ↑ [194 cycles (89 MAC operations, 8 divides) per quad polygon[13] 194 cycles (89 MAC operations, 8 divides) per quad polygon[13]]
- ↑ [206 cycles (95 MAC operations, 8 divides) per quad polygon[13] 206 cycles (95 MAC operations, 8 divides) per quad polygon[13]]
- ↑ [230 cycles (107 MAC operations, 8 divides) per quad polygon[20][21] 230 cycles (107 MAC operations, 8 divides) per quad polygon[20][21]]
- ↑ [388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),[23][24] 496 cycles per 32-pixel polygon (3 cycles per pixel) 388 cycles (309 geometry cycles, 40 RAM cycles, 39 raster operations) 400 cycles per 4-scanline polygon (3 operations/scanline per polygon),[23][24] 496 cycles per 32-pixel polygon (3 cycles per pixel)]
- ↑ [572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
- Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,[25] 2 cycles per pixel)[26]
- Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
- Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)[27] 572 cycles (332 cycles flat shading, 240 cycles texture mapping) per 32-texel polygon
- Flat shading: 332 cycles per 32-pixel polygon (194 geometry cycles, 40 RAM cycles, 34 raster operations,[25] 2 cycles per pixel)[26]
- Texture mapping: 128 cycles per 32-texel texture: 2 block moves, 2 cycles per texel (2 bytes per texel)
- Texture mapping: 112 divide cycles per 32-texel polygon: 56 divides per 32-texel polygon, 24 vertex divide cycles per polygon (12 divides per polygon), 64 texel divide cycles per 32-texel polygon (32 divides, 1 divide per texel)[27]]
- ↑ [628 cycles per 32-texel polygon
- Gouraud shading: 388 cycles per 32-pixel polygon
- Texture mapping: 240 cycles per 32-texel polygon 628 cycles per 32-texel polygon
- Gouraud shading: 388 cycles per 32-pixel polygon
- Texture mapping: 240 cycles per 32-texel polygon]
References
- ↑ 1.0 1.1 Sega Model 1 Hardware Overview (MAME)
- ↑ Mean Machines Sega, "December 1994" (UK; 1994-10-28), page 18
- ↑ 3.0 3.1 Edge, "June 1994" (UK; 1994-04-28), page 47
- ↑ http://www.1up.com/features/disappearance-suzuki-part-1?pager.offset=2 (archive.today)
- ↑ Mean Machines Sega, "May 1994" (UK; 1994-03-xx), page 51
- ↑ Yu Suzuki Interview, Strana Igr, November 2013
- ↑ http://www.thg.ru/smoke/19991022/print.html
- ↑ 8.0 8.1 8.2 TGP (MAME)
- ↑ File:Overview of 32-bit V-Series Microprocessor.pdf
- ↑ File:UPD70616ProgrammersReferenceManual.pdf
- ↑ File:MB89396 datasheet.pdf
- ↑ File:MB89374 datasheet.pdf
- ↑ 13.0 13.1 13.2 13.3 Sega Model 1 Video Hardware (MAME)
- ↑ Sega Model 1 ROM Dump
- ↑ 15.0 15.1 File:MB86232 datasheet.pdf
- ↑ 16.0 16.1 16.2 File:MB86232 datasheet.pdf, page 32
- ↑ MODEL1 (アーケードゲーム基板@ ウィキ)
- ↑ Sega 16‑Bit Common Hardware, MAME
- ↑ Sega System 24 Hardware Notes (2013-06-16)
- ↑ Sega Model 2 Geometry Engine and 3D Rasterizer (MAME)
- ↑ Design of Digital Systems and Devices (pages 95-97)
- ↑ File:GameOn US 06.pdf, page 11
- ↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
- ↑ File:32XUSHardwareManual.pdf, page 76
- ↑ Algorithms for Parallel Polygon Rendering (pages 33-36)
- ↑ Algorithms for Parallel Polygon Rendering (page 35)
- ↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)
- ↑ File:MB8421 datasheet.pdf
- ↑ 29.0 29.1 File:MB8431 datasheet.pdf
- ↑ Virtua Formula (MAME)
- ↑ Virtua Fighter (MAME)
- ↑ 32.0 32.1 32.2 File:M5M5178AP datasheet.pdf
- ↑ 33.0 33.1 File:MB8464A datasheet.pdf
- ↑ MB8432 Datasheet, Fujitsu
- ↑ File:HM658128A datasheet.pdf
- ↑ File:HM65256B datasheet.pdf
- ↑ 37.0 37.1 File:HN27C1024 datasheet.pdf
- ↑ File:MB8316200B datasheet.pdf
- ↑ File:MB834000 datasheet.pdf
- ↑ https://game.watch.impress.co.jp/docs/news/758667.html (Wayback Machine: 2023-11-10 10:30)
- ↑ https://www.4gamer.net/games/999/G999905/20210126043/ (Wayback Machine: 2021-02-05 15:00)
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