Difference between revisions of "Blast processing"

Revision as of 12:56, 13 October 2018

Blast Processing was a marketing term coined by Sega of America to advertise the faster processing performance of the Sega Mega Drive (Sega Genesis in that region) compared to competing platforms at the time, specifically the Super Nintendo Entertainment System.

Sonic the Hedgehog 2 was the posterboy for this campaign, being faster than any other platform game at the time. The ad campaign featured commercials with races between two vehicles, with the Super NES strapped to one and the Genesis strapped to the other.

Sega originally coined the term to refer to the high-speed bandwidth and fillrate of the Mega Drive VDP graphics processor's DMA controller. It was a reference to how the DMA controller could "blast" data into the VDP graphics processor and DAC at high speeds. However, many later assumed it was referring to the 68000 CPU's higher clock rate.

History

Origins

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According to Sega staff involved in its development and marketing, it was the high-speed DMA controller, rather than the CPU clock rate, that the term was actually referring to. According to Sega of America's former technical director Scot Bayless:^[1]

“	the PR guys interviewed me about what made the platform interesting from a technical standpoint and somewhere in there I mentioned the fact that you could just "blast data into the DAC's". Well they loved the word 'blast' and the next thing I knew Blast Processing was born.	„
— Scot Bayless

One of the specific DMA programming techniques he was referring to was the mid-frame palette swap, where the color could be changed every scanline, increasing the colors displayed on screen, a technique that was used in Sonic 2:^[2]

“	Marty Franz [Sega technical director] discovered that you could do this nifty trick with the display system by hooking the scan line interrupt and firing off a DMA at just the right time. The result was that you could effectively jam data onto the graphics chip while the scan line was being drawn – which meant you could drive the DAC's with 8 bits per pixel. Assuming you could get the timing just right you could draw 256 color static images. There were all kinds of subtleties to the timing and the trick didn't work reliably on all iterations of the hardware but you could do it and it was cool as heck.	„
— Scot Bayless

Many of these DMA programmable techniques were originally intended by the Mega Drive's original product designer Masami Ishikawa:^[3]

“	the sprite size could be changed to fill the whole display. It could also display the background screen behind the scrolling window and could change the color of each line. The number of available colors was limited compared to comparable arcade systems, but it could create shadows that matched each character's shape and was also capable of semi-transparency.	„
— Masami Ishikawa

Response

In response to Sega's successful "Blast Processing" marketing campaign in the wake of Sonic the Hedgehog 2 since 1992, Nintendo mounted a successful magazine advertising campaign two years later in 1994. They published an advertisement entitled "SMASHING The Myth About Speed and Power" in popular video game magazines such as Electronic Gaming Monthly, GamePro and Game Players.^[4]^[5]

The advertisement was presented as a two-page, pseudo-editorial piece. While it had the word "advertisement" in very small writing, it was not made clear to readers that it was written by Nintendo, misleading many to believe it was a legitimate editorial piece written by the actual magazines. Nintendo's pseudo-editorial piece claimed that "Blast Processing" is a "Myth" and made a number of other claims intended to make the SNES look technically superior to the Genesis in every way other than the CPU clock rate. However, a number of the claims made in Nintedo's pseudo-editorial advertisement were either inaccurate or misleading:

It claimed that the Genesis did not have any hardware/technology that gave a "Blast" boost. However, the term "Blast Processing" was originally coined to refer to its VDP's DMA controller "blasting" data at higher speeds than the SNES.
It claimed that the SNES was just as fast as the Genesis. To support this claim, it noted that, while the SNES's Ricoh 5A22 CPU has a slower clock rate, it has a faster memory transfer cycle time, claiming that this gives it faster data transfer speed. However, the Mega Drive's 68000 CPU has a wider 16-bit external data bus, twice as wide as the 5A22's 8-bit external data bus, which means the 68000 transfers 16-bit data at a time, whereas the 5A22 transfers 8-bit data at a time, giving the 68000 a faster data transfer speed.
It claimed the SNES's larger RAM gives it superiority in terms of speeding-up programs. However, RAM speed is largely determined by bandwidth. The Genesis has faster RAM bandwidth, making it faster for program access.
It claimed that the Genesis only had a 256-color palette. However, the Genesis has a 512-color palette (or 1536 colors in shadow/highlight mode).
It claimed that the SNES is capable of scaling Sonic. However, Mode 7 only scales backgrounds, not sprites.
It suggested that the Genesis is not capable of scaling or rotation. However, the Genesis is capable of these effects through software programming, by relying on its CPU's faster arithmetic and the VDP's faster DMA controller.
It suggested that only the SNES has specialised DMA hardware capable of high-speed DMA. However, the Genesis has a DMA controller with faster DMA transfer speeds than the SNES.
Its statement that the SNES has a higher sprite display limit is true, but misleading, as it can only reach its display limit when using small sprites. The Genesis displays more sprite tiles and has a higher sprite fillrate, which allows the Genesis to display a higher number of large sprites, as well as a greater variety of sprites.
It claimed that the SNES's Sony SPC sound chip produces sharper audio than the Mega Drive's Yamaha YM2612 sound chip. However, the YM2612 produces a higher sound output frequency of 52 kHz, giving it sharper audio clarity compared to the SPC's 32 kHz output.

Despite these misleading claims and inaccuracies, Nintendo's pseudo-editorial advertisement helped create the perception that Sega's marketing department were being dishonest and that there is no basis for the "Blast Processing" label, leading to backlash against the "Blast Processing" label and a general distrust of Sega's marketing department.

Technical details

For more technical details on Mega Drive, see Mega Drive: Technical specifications and Mega Drive: Blast Processing

The term was used to refer to either the faster CPU processor or the VDP graphics processor's faster DMA controller.

CPU

The main CPU processor was clocked over two times faster than the one in its rival product, the SNES. Sega's Motorola 68000 processor was clocked at 7.67 MHz, compared to the 3.58 MHz clock speed of Nintendo's Ricoh 5A22 processor. However, the idea of simply comparing CPU clock rates to determine performance, regardless of other characteristics, is commonly known as the megahertz myth. While Nintendo's 5A22 did run slower in clock cycles per second, it would put out more instructions per clock cycle, giving it a similar MIPS (million instructions per second) performance to Sega's 68000.

The 68000's faster performance came from other advantages, such as a wider 32-bit internal data bus (compared to the 5A22's 16-bit internal data bus), wider 16-bit external data bus (compared to the 5A22's 8-bit external data bus), faster memory bandwidth, more registers, a more powerful 32-bit instruction set,^[6] faster arithmetic calculations (with more precision), and shared codebase with arcade games (where the 68000 saw widespread use).

Console		Mega Drive	Super NES^[7]^[8]^[9]
Main CPU		Motorola 68000	Ricoh 5A22
Clock rate	Internal	7.670453 MHz (NTSC), 7.600489 MHz (PAL)	2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL)
Clock rate	External	5 MHz (RAM/ROM)	2.660171–2.684658 MHz (RAM), 2.660171–3.579545 MHz (ROM)
Bits	Data bus width	32-bit internal, 16-bit external	16-bit internal, 8-bit external
	Arithmetic logic units	16-bit data ALU, 32-bit address ALU (2x 16-bit ALU)	16-bit ALU
	Word length	16-bit	16-bit
Internal instructions	Registers	16x 32-bit registers	4x 16-bit registers, 4x 8-bit registers
	Instruction set	16-bit, 32-bit	8-bit, 16-bit
	Instructions per second	1.342329 MIPS (NTSC), 1.330085 MIPS (PAL)	1.125–1.5 MIPS (NTSC), 1.114738–1.486318 MIPS (PAL)
Work RAM	Memory	64 KB PSRAM (16-bit, 5.263157 MHz)	128 KB DRAM (8-bit, 2.660171–2.684658 MHz)
	Bandwidth	10.526314 MB/s (5 MB/s CPU access) CPU access per frame: 81 KB (NTSC), 98 KB (PAL)	2.684658 MB/s (NTSC), 2.660171 MB/s (PAL) CPU access per frame: 43 KB (NTSC), 51 KB (PAL)
	CPU transfer	3.835226 MB/s (NTSC), 3.800244 MB/s (PAL)^{[n 1]} Transfer per frame: 62 KB (NTSC), 73 KB (PAL)	2.684658 MB/s (NTSC), 2.660171 MB/s (PAL)^{[n 2]} Transfer per frame: 43 KB (NTSC), 51 KB (PAL)
Cartridge ROM	Memory	128 KB to 8 MB	128 KB to 6 MB
	Bandwidth	10–15.340906 MB/s (5 MB/s CPU access)	2.5–3.579545 MB/s
	CPU transfer	3.835226 MB/s (NTSC), 3.800244 MB/s (PAL)	2.684658–3.579545 MB/s (NTSC), 2.660171–3.546895 MB/s (PAL)^{[n 3]}
Fixed-point arithmetic	Additions	639,000 adds/sec^{[n 4]}	596,000 adds/sec^{[n 5]}
	Multiplications	109,000 multiplies/sec (16×16)^{[n 6]}	65,000 multiplies/sec (16×8),^{[n 7]} 32,000 multiplies/sec (16×16),^{[n 8]} 94,000 multiplies/sec (Mode 7)^{[n 9]}
	Divisions	54,000 divides/sec (16-bit)^{[n 10]}	51,000 divides/sec (16-bit)^{[n 11]}
3D polygon geometry	Base CPU	3300 polys/s	260 polys/s^{[n 12]}
	Cartridge enhancement chips	Sega Virtua Processor (23.01136 MHz) 50,000 polys/s	Super FX (10.738635 MHz)^[16] 10,000 polys/s^{[n 13]}
	Cartridge enhancement chips	Sega Virtua Processor (23.01136 MHz) 50,000 polys/s	Super FX 2 (21.47727 MHz)^[16] 20,000 polys/s

DMA

The Sega Mega Drive's Yamaha YM7101 VDP graphics processor had a powerful DMA controller that could handle DMA (direct memory access) operations at much faster speeds than the SNES.^[6] The Mega Drive could write to VRAM during active display and VBlank,^[17] and had a faster memory bandwidth than the SNES. The quicker DMA transfer rates and bandwidth gave the Mega Drive a faster performance than the SNES,^[8] and helped give the Mega Drive a higher fillrate, higher gameplay resolution, faster parallax scrolling, fast data blitting, and high frame-rate with many moving objects on screen, and allowed it to display more unique tiles (background and sprite tiles) and large sprites (32×32 and higher) on screen, and quickly transfer more unique tiles and large sprites (16×16 and higher) on screen.

The Mega Drive's DMA capabilities also helped give it more flexibility, allowing the hardware to be programmed in various different ways. Combining the CPU's fast arithmetic with the VDP's fast DMA, it could replicate some of the SNES's hardware features with software programming, such as larger 64×64 sprites (combining 32×32 sprites), background scaling and rotation (like the Sega X Board and Mode 7), and direct color (increasing colors on screen). Other programmable capabilities include mid-frame palette swaps (increasing colors per scanline), bitmap framebuffers, sprite scaling and rotation, ray casting, and 3D polygon graphics; the base Mega Drive hardware (without needing any cartridge enhancement chips) could render 3D polygons with a performance comparable to the SNES's optional Super FX (SFX) cartridge enhancement chip,^[18]^[19]^[20]^[21] which itself was significantly outperformed by the Mega Drive's optional Sega Virtua Processor (SVP) cartridge enhancement chip.

The Yamaha VDP's DMA controller is also fast enough to stream data directly from the ROM cartridge without needing to transfer data to the Mega Drive's internal RAM, allowing the ROM cartridge to function like a large extended RAM. An example of one way this can be used is to stream near-CD-quality sound samples directly from the cartridge (using it like extended audio RAM), and then play them through the Yamaha YM2612 sound chip's PCM channel at up to 52 kHz output, allowing near-CD-quality sampling.^[22] In comparison, the Super Nintendo's slower DMA controller cannot stream samples directly from the cartridge, but needs to copy heavily compressed samples to its limited 64 KB audio RAM and then play them through its Sony SPC sound chip at up to 32 kHz output, limiting its sampling quality.

One area where the SNES has a clear advantage is in terms of color palette. While DMA programming techniques such as those mentioned above allow the Mega Drive to either match or approach the 256 on-screen color display of the SNES, the Mega Drive cannot come close to the overall 32,768 selectable color palette of the SNES. When it came to certain types of graphics, however, such as ray casting and 3D polygons, the SNES did not have a color advantage over the Mega Drive.

Console		Mega Drive	Super NES^[7]^[8]^[9]^[23]
DMA controller		Sega 315‑5313 VDP (Yamaha YM7101)	Ricoh 5A22
Clock rate	Internal	13.423294 MHz (NTSC), 13.300856 MHz (PAL)	2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL)
Clock rate	External	RAM: 8–11.764705 MHz (NTSC), 8–8.333333 MHz (PAL) ROM: 5–7.670453 MHz (NTSC), 5–7.600489 MHz (PAL)	RAM: 2.684658 MHz (NTSC), 2.660171 MHz (PAL) ROM: 2.660171–3.579545 MHz
Video RAM	Memory	64 KB VRAM (64 KB FPM DRAM, 256 bytes SAM), 232 bytes VDP cache (CRAM, VSRAM, sprite buffer)	64 KB SRAM, 1056 bytes PPU cache (CGRAM, OAM)
Video RAM	Bandwidth	8–11.764705 MB/s (VRAM), 26.846588 MB/s (VDP cache)	7.15909 MB/s (NTSC), 7.09379 MB/s (PAL)
DMA blitting transfer rate	Inactive display	VRAM: 3.21845 MB/s, 205 bytes per scanline VDP cache: 6.4369 MB/s, 410 bytes per scanline	NTSC: 2.684658 MB/s, 170.5 bytes per scanline PAL: 2.660171 MB/s, 170.5 bytes per scanline
	Active display (VRAM)	320×224: 708.406 KB/s (NTSC), 1.09701 MB/s (PAL) 320×160: 1.437846 MB/s (NTSC), 1.702026 MB/s (PAL)	256×224: 443.228 KB/s (NTSC), 795.11 KB/s (PAL) 256×192: 763.435 KB/s (NTSC), 1.061548 MB/s (PAL)
	Active display (cache)	320×224: 1.416813 MB/s (NTSC), 2.194021 MB/s (PAL) 320×160: 2.875692 MB/s (NTSC), 3.404052 MB/s (PAL)
Fillrate	Video clock rate	13.300856–13.423294 MHz (VDP)	5.320342–5.369317 MHz (PPU)
	Read fillrate	6.650428–6.934358 MPixels/s	5.320342–5.369317 MPixels/s
	Write fillrate (inactive display)	6.4369 MPixels/s, 410 pixels per scanline	5.320342–5.369317 MPixels/s, 341 pixels per scanline
	Write fillrate (active display)	1.416813–2.875692 MPixels/s (NTSC), 2.194021–3.404052 MPixels/s (PAL)	886,457 pixels/s (NTSC), 1.59022 MPixels/s (PAL)
	Tiles on screen (active display)	Display: 1808 tiles Blit per frame: 369 tiles (NTSC), 1070 tiles (PAL)	Display: 1395 tiles (NTSC), 1536 tiles (PAL) Blit per frame: 230 tiles (NTSC), 496 tiles (PAL)
Sprites	Sprite fillrate	4.90887 MTexels/s, 320 texels per scanline	4.282881 MTexels/s, 272 texels per scanline
	Sprite tiles	1280 sprite tiles on screen	512 sprite tiles on screen
	Sprites on screen	80 sprites (8×8 to 32×32), 20 sprites (64×64), 5 sprites (128×128)	128 sprites (8×8, 16×16), 69 sprites (32×32), 17 sprites (64×64), 4 sprites (128×128)
	Unique sprites on screen	80 sprites (8×8 to 32×32), 20 sprites (64×64), 5 sprites (128×128)	128 sprites (8×8, 16×16), 32 sprites (32×32), 8 sprites (64×64), 2 sprites (128×128)
	Blit per frame (NTSC)	80 sprites (8×8 to 16×16), 41 sprites (24×24), 23 sprites (32×32), 5 sprites (64×64)	128 sprites (8×8), 57 sprites (16×16), 14 sprites (32×32), 3 sprites (64×64)
	Blit per frame (PAL)	80 sprites (8×8 to 24×24), 66 sprites (32×32), 16 sprites (64×64), 4 sprites (128×128)	128 sprites (8×8), 124 sprites (16×16), 31 sprites (32×32), 7 sprites (64×64)
	Sprites per scanline	20 sprites (8×8 to 16×16), 13 sprites (24×24), 10 sprites (32×32), 5 sprites (64×64)	32 sprites (8×8), 17 sprites (16×16), 8 sprites (32×32), 4 sprites (64×64)
Background planes	Background tiles on screen	1344–1808 background tiles	256–1024 background tiles
	Tilemap planes	2 scrolling planes (1344–1808 tiles), 1 static window plane, 40–64 overlapping scrolling layers (20–32 layers per plane)	1–4 planes (256–1024 tiles)
	Tilemap resolution	256×256 to 512×512 (2 planes, 1344–1808 tiles), 1024×256 (2 planes, 1344–1424 tiles)	256×256 to 512×512 (1–4 planes, 256–1024 tiles), 1024×1024 (1 plane, 256 tiles)
	Scrolling capabilities	Parallax scrolling, line scrolling, tile scrolling, row/column scrolling, overlapping scrolling layers	Parallax scrolling, line scrolling, tile scrolling
Resolution	Overscan	427×262 (NTSC), 423×312 (PAL)	341×262 (NTSC), 341×312 (PAL)
Resolution	Display resolution	Gameplay: 256×224 to 320×480 (default 320×224) Custom: 128×160 to 320×160, 128×224 to 160×224	Gameplay: 256×224 to 256×239 (default 256×224) Pseudo-hires text: 512×448, 512×478 (half-pixels)
Colors	Color palettes	512 colors (default), 1536 colors (Shadow/Highlight), 4096 colors (static image demo)	32,768 colors (default), 256–4096 colors (direct)
	Colors on screen	61–64 (default), 183–192 (Shadow/Highlight), 256–512 (direct color), 1536 (scrolling background demo)	128–256 (1–2 planes), 128–160 (3 planes), 128 (4 planes), 2723 (static image demo)
	Colors per tile	16 colors (2 planes), 16–256 colors (palette swap), 256–512 colors (direct)	16 colors (1–2 planes), 8 colors (3 planes), 4 colors (4 planes), 256 colors (direct)
3D polygon rendering	Base hardware	1800 polys/s (flat), 1000 polys/s (textured)	190 polys/s (flat),^{[n 14]} 140 polys/s (textured)^{[n 15]}
	Cartridge enhancement chips	Sega Virtua Processor (23.01136 MHz) 20,000 polys/s (flat), 3000 polys/s (textured)	Super FX (10.738635 MHz)^[16] 2000 polys/s (flat),^{[n 16]} 1000 polys/s (textured)^{[n 17]}
	Cartridge enhancement chips		Super FX 2 (21.47727 MHz)^[16] 4000 polys/s (flat), 2000 polys/s (textured)

Notes

↑ [16-bit data bus, 7.670453 MHz (NTSC) or 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte 16-bit data bus, 7.670453 MHz (NTSC) or 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte]
↑ [8-bit data bus, 2.684658 MHz (NTSC), 2.660171 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.684658 MHz (NTSC), 2.660171 MHz (PAL), 1 cycle per byte]
↑ [8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte]
↑ [12 cycles per add^[10] 12 cycles per add^[10]]
↑ [6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)^[11]^[12] 6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)^[11]^[12]]
↑ [70 cycles per multiply^[10] 70 cycles per multiply^[10]]
↑ [55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)^[13]^[12] 55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)^[13]^[12]]
↑ [110 cycles per 16×16 multiply (2x 16×8 multiplies) 110 cycles per 16×16 multiply (2x 16×8 multiplies)]
↑ [38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)^[13]^[12] 38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)^[13]^[12]]
↑ [140 cycles per divide^[10] 140 cycles per divide^[10]]
↑ [70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)^[14]^[12] 70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)^[14]^[12]]
↑ [SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)^[15] SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)^[15]]
↑ [Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),^[15] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide^[16] Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),^[15] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide^[16]]
↑
[SNES CPU rendering:
- Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]
- Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
  - 13.32 kHz geometry per polygon
  - 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]
  - 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup) SNES CPU rendering:
- Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]
- Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
  - 13.32 kHz geometry per polygon
  - 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]
  - 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup)]
↑
[SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)
- 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup
- 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31] SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)
- 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup
- 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31]]
↑
[Super FX rendering:
- Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles
- Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
  - Geometry per polygon: 923 Super FX cycles
  - Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)
  - Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles) Super FX rendering:
- Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles
- Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
  - Geometry per polygon: 923 Super FX cycles
  - Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)
  - Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles)]
↑
[Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)
- 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture
- 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel) Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)
- 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture
- 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)]

References

↑ [Damien McFerran, "Retroinspection: Mega-CD", Retro Gamer, issue 61, page 84 Damien McFerran, "Retroinspection: Mega-CD", Retro Gamer, issue 61, page 84]
↑ The Man Responsible For Sega's Blast Processing (Nintendo Life)
↑ How Sega Built the Genesis: Masami Ishikawa Inteview (Polygon)
↑ ["SMASHING The Myth About Speed and Power" (page 1, page 2) "SMASHING The Myth About Speed and Power" (page 1, page 2)]
↑ File:GamePlayers US 0705.pdf, page 10
↑ ^6.0 ^6.1 Blast Processing 101
↑ ^7.0 ^7.1 SNES hardware specifications
↑ ^8.0 ^8.1 ^8.2 Sega Genesis vs Super Nintendo
↑ ^9.0 ^9.1 Anomie's Register Doc
↑ ^10.0 ^10.1 ^10.2 Standard Instruction Execution Times
↑ SNES Development: General Advice
↑ ^12.0 ^12.1 ^12.2 ^12.3 ^12.4 ^12.5 SNES Development: 65816 Reference
↑ ^13.0 ^13.1 Super NES Programming: Multiplication
↑ Programming the 65816 Including the 6502, 65C02, and 65802
↑ ^15.0 ^15.1 Design of Digital Systems and Devices (pages 95-97)
↑ ^16.0 ^16.1 ^16.2 ^16.3 ^16.4 Super NES Programming: Super FX tutorial
↑ File:GenesisTechnicalOverview.pdf
↑ 3D math engine (SGDK)
↑ Interview: Lee Actor (Sterling Software Programmer)
↑ Star Fox 3D Tech Demo on Sega Genesis
↑ Star Fox 3D Tech Demo on Sega Genesis: Version 2 Using DMA
↑ [Sonic 1: The Next Level Sonic 1: The Next Level]
↑ SNES Developer Manual (Nintendo)
↑ SNES Development: DMA & HDMA
↑ SNES Development: Grog's Guide to DMA and HDMA on the SNES
↑ ^26.0 ^26.1 Algorithms for Parallel Polygon Rendering (pages 33-34)
↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
↑ Algorithms for Parallel Polygon Rendering (page 36)
↑ Computer Organization and Design: The Hardware/Software Interface (page C-44)
↑ Algorithms for Parallel Polygon Rendering (page 35)
↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)

External links

Hardware comparisons
SG-1000 / SC-3000 (specs)	vs. Famicom \| vs. Master System \| vs. C64 \| vs. MSX
Sega Master System (specs)	Hardware comparison \| vs. NES \| vs. Atari 7800 \| vs. Game Gear \| vs. Mega Drive \| vs. C64 and ZX \| vs. Amiga
Sega Mega Drive (specs)	Hardware comparison \| vs. 32X \| vs. Amiga \| vs. Atari Jaguar \| vs. Atari ST \| vs. Mega-CD \| vs. Neo Geo \| vs. Saturn \| vs. SNES \| vs. TurboGrafx-16
Sega Game Gear (specs)	vs. Atari Lynx \| vs. Game Boy \| vs. Master System
Sega Mega-CD (specs)	vs. 32X \| vs. 3DO \| vs. Amiga CD32 \| vs. Atari Jaguar CD \| vs. Neo Geo CD \| vs. SNES \| vs. Saturn \| vs. TurboGrafx-CD
Sega 32X (specs)	Hardware comparison \| vs. 3DO \| vs. Atari Jaguar \| vs. SNES \| vs. Saturn
Sega Saturn (specs)	Hardware comparison \| vs. Atari Jaguar \| vs. Dreamcast \| vs. Nintendo 64 \| vs. PC-FX \| vs. PlayStation \| vs. SNES \| vs. PC \| vs. Sega Model 2
Sega Dreamcast (specs)	Hardware comparison \| vs. GameCube \| vs. Nintendo 64 \| vs. PlayStation \| vs. PlayStation 2 \| vs. Xbox \| vs. Arcade \| vs. PC

Sega Mega Drive
Topics	Technical specifications (Hardware comparison) \| History \| List of games \| Magazine articles \| Promotional material \| Merchandise \| Cartridges \| TradeMark Security System
Hardware	Japan \| North America \| Western Europe \| Eastern Europe \| South America \| Asia \| South Korea \| Australasia \| Africa EZ Games \| Genesis 3 \| LaserActive \| Mega Jet \| Mega PC \| Mega Play \| Mega-Tech System \| Mega 6 \| Nomad \| Teradrive \| Mega Drive Mini \| Mega Drive Mini 2 New Mega Drive \| Tianli VCD/DVD Players \| "Consoles on a chip" \| Licensed clones (Magic 2 \| Mega Game II \| Power Pegasus \| Super Bitman) Unlicensed clones
Add-ons	Game Box \| Power Base Converter \| Mega-CD \| 32X (Mega-CD 32X) \| Mega Modem \| Demo System DS-16
Cases	Sega Genesis Nomad Carrying Case \| System Carry Case
Controllers	Control Pad \| Six Button Control Pad \| 6 Button Arcade Pad \| Arcade Power Stick 6B \| Konami Justifier \| MK-1470 Action Chair \| Activator \| Arcade Power Stick \| Keyboard \| MegaFire \| Mouse \| Mega Stick \| Menacer \| Remote Arcade System \| Ten Key Pad \| Third Party Controllers
Accessories	4 Way Play \| AC adaptor \| Cleaning System \| Control Pad Extension Cord \| Game Factory \| Genesis Speakers \| Headset \| HeartBeat Catalyst \| Microphone \| Region converter cartridges \| Mega Terminal \| Nomad PowerBack \| RF Unit \| SCART Cable \| Stereo Audio Video Cable \| Team Player \| Video Monitor Cable \| Third-party AC adaptors \| Third Party Accessories
Network services	Sega Channel \| Sega Game Toshokan \| Mega Anser \| Mega Net \| TeleBradesco Residência \| XB∀ND
Development tools	ERX 308P \| ERX 318P \| Sprobe \| SNASM68K \| SNASM2 (Mega Drive) \| SNASM2 (32X) \| PSY-Q Development System (Mega Drive) \| PSY-Q Development System (32X) \| 32X CartDev \| Sega Mars Development Aid System \| Sega 32X Development Target
Unreleased	Edge 16 \| Floppy Disk Drive \| Mega Play 1010 \| Sega VR \| Teleplay System \| Video Jukebox

[16-bit_data_bus.2C_7.670453_MHz_.28NTSC.29_or_7.600489_MHz_.28PAL.29.2C_4_cycles_per_word.2C_16-bit_.282_bytes.29_per_word.2C_2_cycles_per_byte-10] [16-bit data bus, 7.670453 MHz (NTSC) or 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte 16-bit data bus, 7.670453 MHz (NTSC) or 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte]

[8-bit_data_bus.2C_2.684658_MHz_.28NTSC.29.2C_2.660171_MHz_.28PAL.29.2C_1_cycle_per_byte-11] [8-bit data bus, 2.684658 MHz (NTSC), 2.660171 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.684658 MHz (NTSC), 2.660171 MHz (PAL), 1 cycle per byte]

[8-bit_data_bus.2C_2.684658.E2.80.933.579545_MHz_.28NTSC.29.2C_2.660171.E2.80.933.546895_MHz_.28PAL.29.2C_1_cycle_per_byte-12] [8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte]

[12_cycles_per_add.7F.27.22.60UNIQ--ref-0000000E-QINU.60.22.27.7F-14] [12 cycles per add^[10] 12 cycles per add^[10]]

[6_cycles_per_add:_17_cycles_per_3_adds_.282_cycles_LDA.2C_6_cycles_CLC.2C_6_cycles_ADC.2C_3_cycles_STA.29.7F.27.22.60UNIQ--ref-00000010-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000011-QINU.60.22.27.7F-17] [6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)^[11]^[12] 6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)^[11]^[12]]

[70_cycles_per_multiply.7F.27.22.60UNIQ--ref-00000013-QINU.60.22.27.7F-18] [70 cycles per multiply^[10] 70 cycles per multiply^[10]]

[55_cycles_per_16.C3.978_multiply_.283_cycles_SEP.2C_6_cycles_STA.2C_3_cycles_STY.2C_12_cycles_NOP.2C_2_cycles_LDA.2C_4_cycles_LDY.2C_6_cycles_XBA.2C_2_cycles_TYA.2C_2_cycles_CLC.2C_2_cycles_ADC.2C_2_cycles_BCC.2C_2_cycles_INY.2C_3_cycles_REP.2C_6_cycles_RTS.29.7F.27.22.60UNIQ--ref-00000015-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000016-QINU.60.22.27.7F-20] [55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)^[13]^[12] 55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)^[13]^[12]]

[110_cycles_per_16.C3.9716_multiply_.282x_16.C3.978_multiplies.29-21] [110 cycles per 16×16 multiply (2x 16×8 multiplies) 110 cycles per 16×16 multiply (2x 16×8 multiplies)]

[38_cycles_per_Mode_7_multiply_.283_cycles_SEP.2C_7_cycles_STA.2C_3_cycles_XBA.2C_6_cycles_STA.2C_6_cycles_STY.2C_3_cycles_REP.2C_2_cycles_LDA.2C_2_cycles_LDY.2C_6_cycles_RTS.29.7F.27.22.60UNIQ--ref-00000019-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000001A-QINU.60.22.27.7F-22] [38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)^[13]^[12] 38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)^[13]^[12]]

[140_cycles_per_divide.7F.27.22.60UNIQ--ref-0000001C-QINU.60.22.27.7F-23] [140 cycles per divide^[10] 140 cycles per divide^[10]]

[70_cycles_per_divide_.283_cycles_STZ.2C_2_cycles_LDY.2C_2_cycles_ASL.2C_2_cycles_BCS.2C_2_cycles_INY.2C_2_cycles_CPY.2C_4_cycles_BNE.2C_7_cycles_ROR.2C_3_cycles_PHA.2C_2_cycles_TXA.2C_2_cycles_SEC.2C_7_cycles_SBC.2C_4_cycles_BCC.2C_2_cycles_TAX.2C_7_cycles_ROL.2C_4_cycles_PLA.2C_7_cycles_LSR.2C_2_cycles_DEY.2C_6_cycles_RTS.29.7F.27.22.60UNIQ--ref-0000001E-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000001F-QINU.60.22.27.7F-25] [70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)^[14]^[12] 70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)^[14]^[12]]

[SNES_CPU_geometry_calculations:_13.32_kHz_per_polygon_.2880_adds.2C_111_multiplies.2C_9_divides.29.7F.27.22.60UNIQ--ref-00000021-QINU.60.22.27.7F-27] [SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)^[15] SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)^[15]]

[Super_FX_geometry_calculations:_923_cycles_per_polygon_.2880_adds.2C_111_multiplies.2C_9_divides.29.2C.7F.27.22.60UNIQ--ref-00000024-QINU.60.22.27.7F_1_cycle_per_add.2C_5_cycles_per_16.C3.9716_multiply.2C_32_cycles_per_16-bit_divide.7F.27.22.60UNIQ--ref-00000025-QINU.60.22.27.7F-29] [Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),^[15] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide^[16] Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),^[15] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide^[16]]

[SNES_CPU_rendering:.0A.2AFramebuffer_rendering:_256.C3.97160_framebuffer_.28double-buffered.2C_40_KB.29.2C_15_FPS_.28614.4_KB.2Fs.29.2C_819.64_kHz_framebuffer_DMA_.281.334_kHz_per_KB.2C.7F.27.22.60UNIQ--ref-00000036-QINU.60.22.27.7F_30_cycles_setup.29.2C_30_cycles_per_DMA_setup_.284_cycles_LDX.2C_6_cycles_STX.2C_8_cycles_LDA.2C_12_cycles_STA.29.7F.27.22.60UNIQ--ref-00000037-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000038-QINU.60.22.27.7F.0A.2APolygon_rendering:_2.759905_MHz_.2815_FPS.29.2C_14.223_kHz_per_8.C3.978_pixel_polygon.0A.2A.2A13.32_kHz_geometry_per_polygon.0A.2A.2A361_Hz_polygon_rendering_per_polygon:_24_comparison_cycles_.2812_comparisons.2C.7F.27.22.60UNIQ--ref-00000039-QINU.60.22.27.7F_2_cycles_per_CPY_comparison.29.2C.7F.27.22.60UNIQ--ref-0000003A-QINU.60.22.27.7F_7_assignments_.286_rasterization_assignments.2C.7F.27.22.60UNIQ--ref-0000003B-QINU.60.22.27.7F_1_flat_shading_assignment.29.2C.7F.27.22.60UNIQ--ref-0000003C-QINU.60.22.27.7F_220_multiply_cycles_.282_multiplies.29.2C_24_add_cycles_.284_adds.29.2C_5_broadcasts.2C.7F.27.22.60UNIQ--ref-0000003D-QINU.60.22.27.7F_110_cycles_DMA_access_.2840_bytes_per_polygon.2C_2_cycles_per_byte.2C_30_cycles_setup.29.7F.27.22.60UNIQ--ref-0000003E-QINU.60.22.27.7F.0A.2A.2A542_Hz_pixel_rendering_per_8.C3.978_pixel_polygon:_384_add_cycles_.281_add_per_pixel.29.2C.7F.27.22.60UNIQ--ref-0000003F-QINU.60.22.27.7F_158_cycles_DMA_.281_byte_per_pixel.2C_2_cycles_per_pixel.2C_30_cycles_setup.29-44] [SNES CPU rendering:
Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]

Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
13.32 kHz geometry per polygon

361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup) SNES CPU rendering:

Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]

Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
13.32 kHz geometry per polygon

361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup)]

[15] Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]

[16] Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
13.32 kHz geometry per polygon

361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup) SNES CPU rendering:

[17] 13.32 kHz geometry per polygon

[18] 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

[19] 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup) SNES CPU rendering:

[20] Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,^[24] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)^[25]^[12]

[21] Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
13.32 kHz geometry per polygon

361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup)]

[22] 13.32 kHz geometry per polygon

[23] 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,^[26] 2 cycles per CPY comparison),^[12] 7 assignments (6 rasterization assignments,^[26] 1 flat shading assignment),^[27] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,^[28] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)^[29]

[24] 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),^[30] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup)]

[SNES_CPU_texture_mapping:_18.746_kHz_per_8.C3.978_texel_polygon_.285.426_kHz_texture_mapping_per_8.C3.978_texel_polygon.29.0A.2A316_cycles_DMA_per_8.C3.978_texel_texture:_2_block_moves.2C_2_cycles_per_texel_.281_byte_per_texel.29.2C_30_cycles_setup.0A.2A5110_divide_cycles_per_8.C3.978_texel_polygon:_73_divides_per_8.C3.978_texel_polygon.2C_630_vertex_divide_cycles_per_polygon_.289_divides_per_polygon.29.2C_4480_texel_divide_cycles_per_8.C3.978_texel_polygon_.2864_divides.2C_1_divide_per_texel.29.7F.27.22.60UNIQ--ref-00000041-QINU.60.22.27.7F-46] [SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)
316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup

5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31] SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)

316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup

5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31]]

[26] 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup

[27] 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31] SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)

[28] 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup

[29] 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)^[31]]

[Super_FX_rendering:.0A.2AFramebuffer_rendering:_256.C3.97192_framebuffer_.28double-buffered.2C_48_KB.29.2C_15_FPS_.28737.28_KB.2Fs.29.2C_983.562_kHz_CPU_framebuffer_DMA_.281.334_kHz_per_KB.2C_30_cycles_setup.29.2C_2.950686_MHz_Super_FX_cycles.0A.2APolygon_rendering:_7.787949_MHz_.2815_FPS.29_Super_FX_cycles_available.2C_3.632_kHz_per_8.C3.978_pixel_polygon.0A.2A.2AGeometry_per_polygon:_923_Super_FX_cycles.0A.2A.2APolygon_rendering_per_polygon:_1083_Super_FX_cycles_.28361_CPU_cycles.29.0A.2A.2APixel_rendering_per_8.C3.978_pixel_polygon:_1626_Super_FX_cycles_.28542_CPU_cycles.29-47] [Super FX rendering:
Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles

Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
Geometry per polygon: 923 Super FX cycles

Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles) Super FX rendering:

Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles

Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
Geometry per polygon: 923 Super FX cycles

Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles)]

[31] Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles

[32] Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
Geometry per polygon: 923 Super FX cycles

Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles) Super FX rendering:

[33] Geometry per polygon: 923 Super FX cycles

[34] Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

[35] Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles) Super FX rendering:

[36] Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles

[37] Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
Geometry per polygon: 923 Super FX cycles

Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles)]

[38] Geometry per polygon: 923 Super FX cycles

[39] Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)

[40] Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles)]

[Super_FX_texture_mapping:_6.916_kHz_per_8.C3.978_texel_polygon_.283.284_kHz_texture_mapping_per_8.C3.978_texel_polygon.29.0A.2A948_Super_FX_cycles_.28316_CPU_cycles.29_DMA_per_8.C3.978_texel_texture.0A.2A2336_divide_cycles_per_8.C3.978_texel_polygon:_73_divides_per_8.C3.978_texel_polygon.2C_288_vertex_divide_cycles_per_polygon_.289_divides_per_polygon.29.2C_2048_texel_divide_cycles_per_8.C3.978_texel_polygon_.2864_divides.2C_1_divide_per_texel.29-48] [Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)
948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture

2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel) Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)

948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture

2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)]

[42] 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture

[43] 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel) Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)

[44] 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture

[45] 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)]

[Damien_McFerran.2C_.22Retroinspection:_Mega-CD.22.2C_.27.27.5B.5Bwikipedia:Retro_Gamer.7CRetro_Gamer.5D.5D.27.27.2C_issue_61.2C_page_84-1] [Damien McFerran, "Retroinspection: Mega-CD", Retro Gamer, issue 61, page 84 Damien McFerran, "Retroinspection: Mega-CD", Retro Gamer, issue 61, page 84]

[.5Bhttp:.2F.2Fwww.nintendolife.com.2Fnews.2F2015.2F11.2Fthe_man_responsible_for_segas_blast_processing_gimmick_is_sorry_for_creating_that_ghastly_phrase_The_Man_Responsible_For_Sega.27s_Blast_Processing.5D_.28.5B.5Bwikipedia:Nintendo_Life.7CNintendo_Life.5D.5D.29-2] The Man Responsible For Sega's Blast Processing (Nintendo Life)

[.5Bhttp:.2F.2Fwww.polygon.com.2Ffeatures.2F2015.2F2.2F3.2F7952705.2Fsega-genesis-masami-ishikawa_How_Sega_Built_the_Genesis:_Masami_Ishikawa_Inteview.5D_.28.5B.5Bwikipedia:Polygon_.28website.29.7CPolygon.5D.5D.29-3] How Sega Built the Genesis: Masami Ishikawa Inteview (Polygon)

[.22SMASHING_The_Myth_About_Speed_and_Power.22_.28.5Bhttp:.2F.2Fwww.gamepilgrimage.com.2Fsites.2Fdefault.2Ffiles.2FNintendoads.2FNintendoad11.JPG_page_1.5D.2C_.5Bhttp:.2F.2Fwww.gamepilgrimage.com.2Fsites.2Fdefault.2Ffiles.2FNintendoads.2FNintendoad12.JPG_page_2.5D.29-4] ["SMASHING The Myth About Speed and Power" (page 1, page 2) "SMASHING The Myth About Speed and Power" (page 1, page 2)]

[:File:GamePlayers_US_0705.pdf_p10-5] File:GamePlayers US 0705.pdf, page 10

[.5Bhttp:.2F.2Ftrixter.oldskool.org.2F2008.2F12.2F05.2Fblast-processing-101.2F_Blast_Processing_101.5D-6] 6.0 ^6.1 Blast Processing 101

[.5Bhttp:.2F.2Fproblemkaputt.de.2Ffullsnes.htm_SNES_hardware_specifications.5D-7] 7.0 ^7.1 SNES hardware specifications

[.5Bhttp:.2F.2Fwww.gamepilgrimage.com.2Fcontent.2Fsega-genesis-vs-super-nintendo_Sega_Genesis_vs_Super_Nintendo.5D-8] 8.0 ^8.1 ^8.2 Sega Genesis vs Super Nintendo

[.5Bhttp:.2F.2Fwww.romhacking.net.2Fdocuments.2F196.2F_Anomie.27s_Register_Doc.5D-9] 9.0 ^9.1 Anomie's Register Doc

[.5Bhttp:.2F.2Foldwww.nvg.ntnu.no.2Famiga.2FMC680x0_Sections.2Ftimstandard.HTML_Standard_Instruction_Execution_Times.5D-13] 10.0 ^10.1 ^10.2 Standard Instruction Execution Times

[.5Bhttps:.2F.2Fwiki.superfamicom.org.2Fsnes.2Fshow.2FGeneral.2BAdvice_SNES_Development:_General_Advice.5D-15] SNES Development: General Advice

[.5Bhttps:.2F.2Fwiki.superfamicom.org.2Fsnes.2Fshow.2F65816.2BReference_SNES_Development:_65816_Reference.5D-16] 12.0 ^12.1 ^12.2 ^12.3 ^12.4 ^12.5 SNES Development: 65816 Reference

[.5Bhttps:.2F.2Fen.wikibooks.org.2Fwiki.2FSuper_NES_Programming.2Fmultiplication_Super_NES_Programming:_Multiplication.5D-19] 13.0 ^13.1 Super NES Programming: Multiplication

[.5Bhttp:.2F.2Fapprize.info.2Fprogramming.2F65816.2F17.html_Programming_the_65816_Including_the_6502.2C_65C02.2C_and_65802.5D-24] Programming the 65816 Including the 6502, 65C02, and 65802

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DiAvHt5RCHbMC.26pg.3DPA95_.27.27Design_of_Digital_Systems_and_Devices.27.27_.28pages_95-97.29.5D-26] 15.0 ^15.1 Design of Digital Systems and Devices (pages 95-97)

[.5Bhttps:.2F.2Fen.wikibooks.org.2Fwiki.2FSuper_NES_Programming.2FSuper_FX_tutorial_Super_NES_Programming:_Super_FX_tutorial.5D-28] 16.0 ^16.1 ^16.2 ^16.3 ^16.4 Super NES Programming: Super FX tutorial

[:File:GenesisTechnicalOverview.pdf_p-30] File:GenesisTechnicalOverview.pdf

[.5Bhttps:.2F.2Fgithub.com.2FStephane-D.2FSGDK.2Fblob.2Fmaster.2Finc.2Fmaths3D.h_3D_math_engine_.28SGDK.29.5D-31] 3D math engine (SGDK)

[.5Bhttp:.2F.2Fwww.sega-16.com.2F2008.2F05.2Finterview-lee-actor.2F_Interview:_Lee_Actor_.28Sterling_Software_Programmer.29.5D-32] Interview: Lee Actor (Sterling Software Programmer)

[.5Bhttps:.2F.2Fyoutu.be.2FYUZpF2JLF4s_Star_Fox_3D_Tech_Demo_on_Sega_Genesis.5D-33] Star Fox 3D Tech Demo on Sega Genesis

[.5Bhttps:.2F.2Fyoutu.be.2FoHLc0AzD85g_Star_Fox_3D_Tech_Demo_on_Sega_Genesis:_Version_2_Using_DMA.5D-34] Star Fox 3D Tech Demo on Sega Genesis: Version 2 Using DMA

[.27.27Sonic_1:_The_Next_Level.27.27-35] [Sonic 1: The Next Level Sonic 1: The Next Level]

[.5Bhttp:.2F.2Fwww.romhacking.net.2Fdocuments.2F196.2F_SNES_Developer_Manual.5D_.28.5B.5BNintendo.5D.5D.29-36] SNES Developer Manual (Nintendo)

[.5Bhttps:.2F.2Fwiki.superfamicom.org.2Fsnes.2Fshow.2FDMA.2B.2526.2BHDMA_SNES_Development:_DMA_.26_HDMA.5D-37] SNES Development: DMA & HDMA

[.5Bhttps:.2F.2Fwiki.superfamicom.org.2Fsnes.2Fshow.2FGrog.27s.2BGuide.2Bto.2BDMA.2Band.2BHDMA.2Bon.2Bthe.2BSNES_SNES_Development:_Grog.27s_Guide_to_DMA_and_HDMA_on_the_SNES.5D-38] SNES Development: Grog's Guide to DMA and HDMA on the SNES

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DyiVRHrxFj2wC.26pg.3DPA33_.27.27Algorithms_for_Parallel_Polygon_Rendering.27.27_.28pages_33-34.29.5D-39] 26.0 ^26.1 Algorithms for Parallel Polygon Rendering (pages 33-34)

[.5Bhttp:.2F.2Fsirkan.iit.bme.hu.2F.7Eszirmay.2Fabbas.pdf.23page.3D53_Transformation_Of_Rendering_Algorithms_For_Hardware_Implementation_.28page_53.29.5D-40] Transformation Of Rendering Algorithms For Hardware Implementation (page 53)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DyiVRHrxFj2wC.26pg.3DPA36_.27.27Algorithms_for_Parallel_Polygon_Rendering.27.27_.28page_36.29.5D-41] Algorithms for Parallel Polygon Rendering (page 36)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DEVhgAAAAQBAJ.26pg.3DSL3-PA44_.27.27Computer_Organization_and_Design:_The_Hardware.2FSoftware_Interface.27.27_.28page_C-44.29.5D-42] Computer Organization and Design: The Hardware/Software Interface (page C-44)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DyiVRHrxFj2wC.26pg.3DPA35_.27.27Algorithms_for_Parallel_Polygon_Rendering.27.27_.28page_35.29.5D-43] Algorithms for Parallel Polygon Rendering (page 35)

[.5Bhttps:.2F.2Fbooks.google.co.uk.2Fbooks.3Fid.3DteMHqC2BnuYC.26pg.3DPA110_.27.27State_of_the_Art_in_Computer_Graphics:_Visualization_and_Modeling.27.27_.28page_110.29.5D-45] State of the Art in Computer Graphics: Visualization and Modeling (page 110)

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@@ Line 149: / Line 149: @@
 The Mega Drive's DMA capabilities also helped give it more flexibility, allowing the hardware to be programmed in various different ways. Combining the CPU's fast arithmetic with the VDP's fast DMA, it could replicate some of the SNES's hardware features with software programming, such as larger 64×64 sprites (combining 32×32 sprites), background scaling and rotation (like the [[Sega X Board]] and [[wikipedia:Mode 7|Mode 7]]), and direct color (increasing colors on screen). Other programmable capabilities include mid-frame palette swaps (increasing colors per scanline), [[wikipedia:Bitmap|bitmap]] [[wikipedia:Framebuffer|framebuffers]], sprite scaling and rotation, [[wikipedia:Ray casting|ray casting]], and 3D polygon graphics; the base Mega Drive hardware (without needing any [[cartridge]] enhancement chips) could render 3D polygons with a performance comparable to the SNES's optional [[wikipedia:Super FX|Super FX]] (SFX) cartridge enhancement chip,{{ref|[https://github.com/Stephane-D/SGDK/blob/master/inc/maths3D.h 3D math engine (SGDK)]}}{{ref|[http://www.sega-16.com/2008/05/interview-lee-actor/ Interview: Lee Actor (Sterling Software Programmer)]}}{{ref|[https://youtu.be/YUZpF2JLF4s Star Fox 3D Tech Demo on Sega Genesis]}}{{ref|[https://youtu.be/oHLc0AzD85g Star Fox 3D Tech Demo on Sega Genesis: Version 2 Using DMA]}} which itself was significantly outperformed by the Mega Drive's optional [[Sega Virtua Processor]] (SVP) cartridge enhancement chip.
-The Yamaha VDP's DMA controller is also fast enough to stream data directly from the [[ROM]] [[cartridge]] without needing to transfer data to the Mega Drive's internal [[RAM]], allowing the ROM cartridge to function like a large extended RAM. An example of one way this can be used is to stream near-CD-quality sound samples directly from the cartridge (using it like extended audio RAM), and then play them through the Yamaha [[YM2612]] sound chip's [[PCM]] channel at 52 kHz output, allowing near-CD-quality sampling.{{ref|''Sonic 1: The Next Level''}} In comparison, the Super Nintendo's slower DMA controller cannot stream samples directly from the cartridge, but needs to copy heavily compressed samples to its limited 64 KB audio RAM and then play them through its [[Sony]] SPC sound chip's 32 kHz output, greatly limiting its sampling quality.
+The Yamaha VDP's DMA controller is also fast enough to stream data directly from the [[ROM]] [[cartridge]] without needing to transfer data to the Mega Drive's internal [[RAM]], allowing the ROM cartridge to function like a large extended RAM. An example of one way this can be used is to stream near-CD-quality sound samples directly from the cartridge (using it like extended audio RAM), and then play them through the Yamaha [[YM2612]] sound chip's [[PCM]] channel at up to 52 kHz output, allowing near-CD-quality sampling.{{ref|''Sonic 1: The Next Level''}} In comparison, the Super Nintendo's slower DMA controller cannot stream samples directly from the cartridge, but needs to copy heavily compressed samples to its limited 64 KB audio RAM and then play them through its [[Sony]] SPC sound chip at up to 32 kHz output, limiting its sampling quality.
 One area where the SNES has a clear advantage is in terms of color palette. While DMA programming techniques such as those mentioned above allow the Mega Drive to either match or approach the 256 on-screen color display of the SNES, the Mega Drive cannot come close to the overall 32,768 selectable color palette of the SNES. When it came to certain types of graphics, however, such as ray casting and 3D polygons, the SNES did not have a color advantage over the Mega Drive.