Blast processing

From Sega Retro

Blast processing was a marketing term coined by Sega of America to promote the Sega Mega Drive (Sega Genesis in that region) video game console over its nearest rival, the Super Nintendo Entertainment System. The idea was to pitch the Super NES as the slower of the two machines, so that consumers would purchase a Genesis instead.

While the campaign was short-lived, it was extremely successful in making the Genesis a more desirable product in 1992 and 1993, and remains a talking point among fans to this day. It was not until the 2000s, however, that former Sega staff eventually revealed "blast processing" specifically referred to the Yamaha YM7101 VDP graphics processor's DMA unit.

History

Advertising

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“ The Sega Genesis has blast processing. Super Nintendo, doesn't. „

— US television advert[1]



While the term would be used several times across Sega's marketing output, "blast processing" is usually remembered in North America for appearing in a 30-second commercial by Sega's choice of marketing agency, Goodby Silverstein & Partners. A Genesis (linked up to a TV) is strapped to a high-speed drag racer, while a Super NES is strapped to an old van. A drag race occurs, with the Genesis speeding off, displaying footage from Sonic the Hedgehog 2, Ecco the Dolphin and Streets of Rage 2. The Super NES, however, stutters while Super Mario Kart plays. Inevtiably the Genesis "wins".

The advert wasn't designed to cause people to think about what was being said, just that Sega and the Genesis were "better" than Nintendo and the Super NES. These sorts of "attack ads" were commonplace in the US at the time - other countries with stricter advertising regulations would not be able to air it, not least because it is a difficult to prove the truthfulness of what was being said. The term was not officially used outside of North America, likely for this reason.

Explanation

In the 2000s, former Sega staff revealed that "blast processing" specifically referred to the Yamaha YM7101 VDP graphics processor's DMA unit, which was capable of high-speed DMA, bandwidth and fillrate. It was a reference to how the DMA unit could quickly "blast" data into the VDP graphics processor and the DAC through high-speed DMA (direct memory access). However, due to a lack of explanation (or understanding) from Sega's marketing department in the 1990s, much of the gaming media in the 1990s had assumed it was referring to the 68000 CPU's higher clock rate. This misconception was widespread up until the 2000s, when former Sega staff eventually revealed that "Blast Processing" was originally a reference to the VDP's DMA unit:



“ the PR guys interviewed me about what made the platform interesting from a technical standpoint and somewhere in there I mentioned the fact that you could just "blast data into the DAC's". Well they loved the word 'blast' and the next thing I knew Blast Processing was born. „

— Scot Bayless[2]


One of the specific DMA programming techniques he was referring to was the mid-frame palette swap, where the color could be changed every scanline, increasing the colors displayed on screen, a technique that was used in Sonic 2:



“ Marty Franz [Sega technical director] discovered that you could do this nifty trick with the display system by hooking the scan line interrupt and firing off a DMA at just the right time. The result was that you could effectively jam data onto the graphics chip while the scan line was being drawn – which meant you could drive the DAC's with 8 bits per pixel. Assuming you could get the timing just right you could draw 256 color static images. There were all kinds of subtleties to the timing and the trick didn't work reliably on all iterations of the hardware but you could do it and it was cool as heck. „

— Scot Bayless[3]


Many of these DMA programmable techniques were originally intended by the Mega Drive's original product designer Masami Ishikawa:



“ the sprite size could be changed to fill the whole display. It could also display the background screen behind the scrolling window and could change the color of each line. The number of available colors was limited compared to comparable arcade systems, but it could create shadows that matched each character's shape and was also capable of semi-transparency. „

— Masami Ishikawa[4]



As with many marketing buzzwords from the era, "blast processing" was a questionable term in the 1990s, up until these interviews in the 2000s eventually revealed that the term was actually referring to the DMA unit. It is also worth noting that, while the Mega Drive is able to process data more quickly than the Super NES, the quality of the software lies in the hands of individual developers. The Mega Drive hardware was not pushed to its limits in the 1990s, but it was not until the 2000s and 2010s that the homebrew development community were able to push the system to its limits.

Response

While the "blast processing" term went largely unchallenged for over a year, Nintendo eventually responded to it in a series of magazine campaigns in 1994. Most notably, they published an advertisement entitled "SMASHING The Myth About Speed and Power" in popular US video game magazines such as Electronic Gaming Monthly, GamePro and Game Players which aimed to counter Sega's narrative.[5]

The advertisement was presented as a two-page, pseudo-editorial piece. While it had the word "advertisement" in very small writing, it was not made clear to readers that it was written by Nintendo, misleading many to believe it was a legitimate editorial piece written by the actual magazines. Nintendo's pseudo-editorial piece claimed that "Blast Processing" is a "Myth" and made a number of other claims intended to make the SNES look technically superior to the Genesis in every way other than the CPU clock rate. While some of the claims were accurate, there were a number of claims made in Nintedo's pseudo-editorial advertisement which were either inaccurate, uninformed or misleading:

  • It claimed that the Genesis did not have any hardware/technology that gave a "Blast" boost. However, the term "Blast Processing" was originally coined to refer to its VDP's DMA unit "blasting" data at higher speeds than the SNES. But it's unlikely that Nintendo could've known this at the time, due to a lack of explanation from Sega's own marketing department in the 1990s.
  • It claimed that the SNES was just as fast as the Genesis. To support this claim, it noted that, while the SNES's Ricoh 5A22 CPU has a slower clock rate, it has faster memory transfer per cycle, claiming that this gives it faster data transfer speed. However, the Mega Drive's 68000 CPU has a wider 16-bit external data bus, twice as wide as the 5A22's 8-bit external data bus, which means the 68000 transfers 16-bit data per cycle, whereas the 5A22 transfers 8-bit data per cycle, giving the 68000 a faster data transfer speed.
  • It claimed the SNES's larger RAM gives it superiority in terms of speeding-up programs. However, RAM speed is largely determined by bandwidth. The Genesis has faster RAM bandwidth, making it faster for program access. Furthermore, it can read program data from the ROM cartridge at a higher speed than the SNES.
  • It claimed that the Genesis only had a 256-color palette. However, the Genesis has a 512-color palette, which can be increased to 1536 colors in shadow/highlight mode. With DMA, it can be further increased up to 4096 colors for static images. Nevertheless, the SNES did have a larger palette of up to 32,768 colors.
  • It claimed that the SNES is capable of scaling Sonic. However, Mode 7 only scales backgrounds, not sprites. The SNES usually required enhancement chips such as the SuperFX to achieve true sprite-scaling.
  • It suggested that the Genesis is not capable of scaling or rotation. However, the Genesis is capable of scaling and rotation through software programming, by relying on its CPU's fast arithmetic and the VDP's fast DMA unit.
  • It suggested that only the SNES has specialised DMA hardware capable of high-speed DMA. However, the Genesis has a DMA unit with faster DMA transfer speeds than the SNES.
  • Its statement that the SNES has a higher sprite display limit is true, but misleading, as it can only reach its display limit when using small sprites. The Genesis displays more sprite tiles and has a higher sprite fillrate, which allows the Genesis to display a higher number of large sprites, as well as a greater variety of sprites.
  • Its claim that the SNES produces sharper sound than the Genesis is not true, as the Mega Drive's Yamaha YM2612 sound chip produces a higher 53 kHz output than the Super Nintendo's Sony chip which produces a 32 kHz output, and the latter's Gaussian filtering limits its frequency range, resulting in a more muffled sound on the SNES and sharper audio clarity on the Genesis.
  • Its implication that only the SNES has true digital sound is not true, as the Mega Drive's YM2612 chip is also capable of true digital sound. It can play PCM samples at up to 8-bit 32 kHz, slightly below the Super Nintendo's 16-bit 32 kHz limit. The Genesis can also stream PCM audio at a comparable bitrate with significantly less bandwidth usage.

Many of these misleading claims and inaccuracies were widely accepted and went largely unchallenged in the 1990s. Nintendo's pseudo-editorial advertisement helped create the perception that Sega's marketing department were being dishonest and that there is no basis for the "Blast Processing" label, leading to backlash against the "Blast Processing" label and a general distrust of Sega's marketing department.

Technical details

For more technical details on Mega Drive, see Mega Drive: Technical specifications and Mega Drive: Blast processing

CPU

The Mega Drive's main CPU (central processing unit) was clocked over two times faster than the one in its rival product, the SNES. Sega's Motorola 68000 processor was clocked at 7.67 MHz, compared to the 3.58 MHz clock speed of Nintendo's Ricoh 5A22 CPU processor. However, the idea of simply comparing CPU clock rates to determine performance, regardless of other characteristics, is commonly known as the megahertz myth. While the 5A22 did run slower in clock cycles per second, it required less clock cycles for most instructions, giving it an overall comparable MIPS (million instructions per second) performance to the 68000. In other words, the 68000's higher clock rate was not the reason the 68000 performed faster than the 5A22.

The 68000's overall faster performance came from other advantages, such as a wider 32-bit internal data bus (double the 5A22's 16-bit internal data bus), wider 16-bit external data bus (double the 5A22's 8-bit external data bus), faster memory bandwidth, more registers, a more powerful 32-bit instruction set,[6] and faster arithmetic calculations (with more precision). It also had a shared codebase with arcade games, where the 68000 saw widespread use.

Console Sega Mega Drive[7] Super Nintendo[8][9][10][11]
Main CPU Motorola 68000 Ricoh 5A22
Clock rate NTSC 7.670453 MHz 2.684658–3.579545 MHz
PAL 7.600489 MHz 2.660171–3.546895 MHz
Bits Data bus width 32-bit internal, 16-bit external 16-bit internal, 8-bit external
Arithmetic logic
units 		16-bit data ALU,
32-bit address ALU (2x 16-bit ALU) 		16-bit ALU
Word length 16-bit 16-bit
Internal
instructions 		Registers 16x 32-bit registers 4x 16-bit registers, 4x 8-bit registers
Instruction set 16-bit, 32-bit 8-bit, 16-bit
Instructions per
second 		1.342329 MIPS (NTSC),
1.330085 MIPS (PAL) 		1.125–1.5 MIPS (NTSC),
1.114738–1.486318 MIPS (PAL)
Work RAM Memory 64 KB PSRAM
(16-bit, 5.263157 MHz) 		128 KB DRAM
(8-bit, 2.660171–2.684658 MHz)
Bandwidth 10.526314 MB/s 2.684658 MB/s (NTSC), 2.660171 MB/s (PAL)
CPU access (NTSC) 3.835226 MB/s,[n 1] 62 KB per frame 2.684658 MB/s,[n 2] 43 KB per frame
CPU access (PAL) 3.800244 MB/s,[n 3] 73 KB per frame 2.660171 MB/s,[n 4] 51 KB per frame
Cartridge
ROM 		Memory 128 KB to 8 MB 128 KB to 6 MB
Bandwidth 10–15.340906 MB/s 2.5–3.579545 MB/s
CPU access 3.835226 MB/s (NTSC),
3.800244 MB/s (PAL) 		2.684658–3.579545 MB/s (NTSC),
2.660171–3.546895 MB/s (PAL)[n 5]
Fixed-point
arithmetic 		Additions 639,000 adds/sec[n 6] 596,000 adds/sec[n 7]
Multiplications 109,000 multiplies/sec (16×16)[n 8] 65,000 multiplies/sec (16×8),[n 9]
32,000 multiplies/sec (16×16),[n 10]
94,000 multiplies/sec (Mode 7)[n 11]
Divisions 54,000 divides/sec (16-bit)[n 12] 51,000 divides/sec (16-bit)[n 13]
3D polygon
geometry calculations 		Base CPU 3300 polys/s 260 polys/s[n 14]
Cartridge
enhancement
chips 		Sega Virtua Processor (23.01136 MHz)
50,000 polys/s 		Super FX (10.738635 MHz)[18]
10,000 polys/s[n 15]
Super FX 2 (21.47727 MHz)[18]
20,000 polys/s
Audio CPU Zilog Z80 Sony SPC700
Clock rate NTSC 3.579545 MHz 1.024 MHz
PAL 3.546894 MHz 1.024 MHz
Bits Bus width 8-bit 8-bit
Word length 8-bit 8-bit
Instruction set 8-bit, 16-bit 8-bit, 16-bit
Instructions per
second 		NTSC 0.519034 MIPS 0.44032 MIPS[19]
PAL 0.5143 MIPS 0.44032 MIPS
Sound RAM Memory 8 KB SRAM/XRAM (8-bit, 3.030303 MHz) 64 KB SRAM (8-bit, 1.024 MHz)
Bandwidth 3.030303 MB/s 1.024 MB/s
Memory access Addressable memory 8 KB sound RAM,
64 KB work RAM (32 KB banks),
128 KB to 8 MB cartridge ROM (32 KB banks) 		64 KB sound RAM
RAM access bandwidth 1.193182 MB/s (NTSC),
1.182298 MB/s (PAL)[20] 		1.024 MB/s
Cartridge ROM
access bandwidth 		1.191969 MB/s (NTSC), 1.181096 MB/s (PAL) 128 KB/s[21]

DMA

The Sega Mega Drive's Yamaha YM7101 VDP graphics processor had a powerful DMA unit that could handle DMA (direct memory access) operations at significantly faster speeds than the SNES.[6] The Mega Drive's DMA unit is part of the VDP, which is located on the same Yamaha IC6 integrated circuit as the sound chips.[22] In comparison, the Super Nintendo's DMA unit is part of its Ricoh 5A22 CPU.[9]

The Mega Drive could write to VRAM during active display, VBlank, and HBlank,[23] whereas the SNES could only do so during VBlank and HBlank. The Mega Drive had higher memory bandwidth and was capable of quicker DMA transfer rates, giving it a faster performance than the SNES,[10] and helped give the Mega Drive a higher fillrate, higher gameplay resolution, faster parallax scrolling, fast data blitting, and high frame-rate with many moving objects on screen, and allowed it to display more unique tiles (background and sprite tiles) and large sprites (32×32 and higher) on screen, and quickly transfer more unique tiles and large sprites (16×16 and higher) on screen.

The Mega Drive's DMA capabilities also helped give it more flexibility, allowing the hardware to be programmed in various different ways. Combining the CPU's fast arithmetic with the VDP's fast DMA, it could replicate some of the SNES's hardware features with software programming, such as larger 64×64 sprites (combining 32×32 sprites), background scaling and rotation (like the Sega X Board and Mode 7), and direct color (increasing colors on screen). Other programmable capabilities include mid-frame palette swaps (increasing colors per scanline), bitmap framebuffers, sprite scaling and rotation, ray casting, and 3D polygon graphics; the base Mega Drive hardware (without needing any cartridge enhancement chips) could render 3D polygons with a performance comparable to the SNES's optional Super FX (SFX) cartridge enhancement chip,[24][25][26][27] which itself was significantly outperformed by the Mega Drive's optional Sega Virtua Processor (SVP) cartridge enhancement chip.

One aspect of the SNES hardware that the Mega Drive cannot replicated with DMA is its color palette. While DMA programming techniques such as those mentioned above could allow the Mega Drive to either match or approach the 256 on-screen color display of the SNES, the Mega Drive cannot come close to the overall 32,768 selectable color palette of the SNES. But when in direct color mode (required for certain types of three-dimensional graphics, such as ray casting and 3D polygons), the SNES and Mega Drive were both on-par in terms of colors (as the SNES cannot use its 32,768 color palette in direct color mode).

Console Sega Mega Drive[7] Super Nintendo[8][9][10][11][28]
System
master
clock rate 		NTSC 53.693175 MHz 21.47727 MHz
PAL 53.203424 MHz 21.28137 MHz
Graphics processing unit (GPU) Sega 315‑5313 VDP (Yamaha YM7101) Ricoh S-PPU (PPU1 & PPU2)
Clock rate NTSC 13.423294 MHz 5.579545 MHz (PPU1), 3.579545 MHz (PPU2)
PAL 13.300856 MHz 5.320343 MHz (PPU1), 3.546895 MHz (PPU2)
Internal
GPU cache 		Cache 232 bytes
(72 bytes CRAM, 80 bytes VSRAM, 80 bytes sprite buffer) 		1056 bytes
(544 bytes PPU1 OAM, 512 bytes PPU2 CGRAM)
Bandwidth 26.846588 MB/s (NTSC), 26.601712 MB/s (PAL) PPU1 OAM:
11.15909 MB/s (NTSC), 10.640685 MB/s (PAL)
PPU2 CGRAM:
7.15909 MB/s (NTSC), 7.09379 MB/s (PAL)
Video RAM
(VRAM) 		Memory 64 KB VRAM (Dual-Port)
(64 KB FPM DRAM, 256 bytes SAM buffer) 		64 KB SRAM (PPU1 VRAM)
Bandwidth 13.423294 MB/s (NTSC), 13.300856 MB/s (PAL) 11.15909 MB/s (NTSC), 10.640685 MB/s (PAL)
DMA controller Sega 315‑5313 VDP (Yamaha YM7101) DMA unit Ricoh 5A22 (CPU) DMA unit
Clock rate NTSC 13.423294 MHz 2.684658–3.579545 MHz
PAL 13.300856 MHz 2.660171–3.546895 MHz
DMA blitting
transfer rate 		VBlank
(inactive display) 		VRAM: 3.21845 MB/s, 205 bytes per scanline
VDP cache: 6.4369 MB/s, 410 bytes per scanline 		NTSC: 2.684658 MB/s, 170.5 bytes per scanline
PAL: 2.660171 MB/s, 170.5 bytes per scanline
HBlank/Active display
(VRAM) 		320×224: 708.406 KB/s (NTSC), 1.09701 MB/s (PAL)
320×160: 1.437846 MB/s (NTSC), 1.702026 MB/s (PAL) 		256×224: 443.228 KB/s (NTSC), 795.11 KB/s (PAL)
256×192: 763.435 KB/s (NTSC), 1.061548 MB/s (PAL)
HBlank/Active display
(cache) 		320×224: 1.416813 MB/s (NTSC), 2.194021 MB/s (PAL)
320×160: 2.875692 MB/s (NTSC), 3.404052 MB/s (PAL)
Fillrate Read fillrate 6.650428–6.934358 MPixels/s 5.320342–5.369317 MPixels/s
Write fillrate
(VBlank/inactive display) 		6.4369 MPixels/s,
410 pixels per scanline 		5.320342–5.369317 MPixels/s,
341 pixels per scanline
Write fillrate
(HBlank/active display) 		1.416813–2.875692 MPixels/s (NTSC),
2.194021–3.404052 MPixels/s (PAL) 		886,457 pixels/s (NTSC),
1.59022 MPixels/s (PAL)
Tiles on screen
(HBlank/active display) 		Display: 1808 tiles
Blit per frame: 369 tiles (NTSC), 1070 tiles (PAL) 		Display: 1395 tiles (NTSC), 1536 tiles (PAL)
Blit per frame: 230 tiles (NTSC), 496 tiles (PAL)
Sprites Sprite fillrate 4.90887 MTexels/s, 320 texels per scanline 4.282881 MTexels/s, 272 texels per scanline
Sprite tiles 1280 sprite tiles on screen 512 sprite tiles on screen
Sprites on
screen 		80 sprites (8×8 to 32×32), 20 sprites (64×64),
5 sprites (128×128) 		128 sprites (8×8, 16×16), 69 sprites (32×32),
17 sprites (64×64), 4 sprites (128×128)
Unique sprites
on screen 		80 sprites (8×8 to 32×32), 20 sprites (64×64),
5 sprites (128×128) 		128 sprites (8×8, 16×16), 32 sprites (32×32),
8 sprites (64×64), 2 sprites (128×128)
Blit per frame
(NTSC) 		80 sprites (8×8 to 16×16), 41 sprites (24×24),
23 sprites (32×32), 5 sprites (64×64) 		128 sprites (8×8), 57 sprites (16×16),
14 sprites (32×32), 3 sprites (64×64)
Blit per frame
(PAL) 		80 sprites (8×8 to 24×24), 66 sprites (32×32),
16 sprites (64×64), 4 sprites (128×128) 		128 sprites (8×8), 124 sprites (16×16),
31 sprites (32×32), 7 sprites (64×64)
Sprites per
scanline 		20 sprites (8×8 to 16×16), 13 sprites (24×24),
10 sprites (32×32), 5 sprites (64×64) 		32 sprites (8×8), 17 sprites (16×16),
8 sprites (32×32), 4 sprites (64×64)
Background
planes 		Background tiles
on screen 		1344–1808 background tiles 256–1024 background tiles
Tilemap planes 2 scrolling planes (1344–1808 tiles),
1 static window plane,
20–32 overlapping scrolling layers per scrolling plane 		1–4 planes (256–1024 tiles)
Tilemap
resolution 		256×256 to 512×512 (2 planes, 1344–1808 tiles),
1024×256 (2 planes, 1344–1424 tiles) 		256×256 to 512×512 (1–4 planes, 256–1024 tiles),
1024×1024 (1 plane, 256 tiles)
Scrolling
capabilities 		Parallax scrolling, line scrolling, tile scrolling,
row/column scrolling, overlapping scrolling layers 		Parallax scrolling, line scrolling, tile scrolling
Scaling and rotation DMA software rendering Mode 7 hardware rendering
Resolution Overscan 427×262 (NTSC), 423×312 (PAL) 341×262 (NTSC), 341×312 (PAL)
Display
resolution 		Gameplay: 256×224 to 320×480 (default 320×224)
DMA: 128×224 to 320×480 		Gameplay: 256×224 to 256×239 (default 256×224)
Pseudo-hires text: 512×448, 512×478 (half-pixels)
Colors Color palette 512 colors (default),
1536 colors (Shadow/Highlight),
4096 colors (DMA bitmap image) 		32,768 colors (default),
256–4096 colors (direct color)
Colors on screen 61–64 (default), 183–192 (Shadow/Highlight) 128–256 (1–2 planes), 128–160 (3 planes),
128 (4 planes)
DMA colors
on screen 		256–512 (direct color), 1536 (scrolling image),
4096 (static image) 		256-512 (direct color), 2723 (static image)
Colors per tile 16 colors (2 planes),
16–256 colors (DMA palette swap),
256–512 colors (DMA direct color) 		16 colors (1–2 planes), 8 colors (3 planes),
4 colors (4 planes), 256 colors (DMA direct color)
3D polygon
rendering 		Base hardware 1800 polys/s (flat), 1000 polys/s (textured) 190 polys/s (flat),[n 16] 140 polys/s (textured)[n 17]
Cartridge
enhancement
chips 		Sega Virtua Processor (23.01136 MHz)
20,000 polys/s (flat), 3000 polys/s (textured) 		Super FX (10.738635 MHz)[18]
2000 polys/s (flat),[n 18] 1000 polys/s (textured)[n 19]
Super FX 2 (21.47727 MHz)[18]
4000 polys/s (flat), 2000 polys/s (textured)
Sound chip(s) Yamaha YM2612, Sega PSG Sony S-DSP
Clock rates System master
clock rate 		53.693175 MHz (NTSC), 53.203424 MHz (PAL) 24.576 MHz
Chip clock rate YM2612: 7.670453 MHz (NTSC), 7.600489 MHz (PAL)
PSG: 3.579545 MHz (NTSC), 3.546894 MHz (PAL) 		2.048 MHz
Sound output Speakers Mono, stereo Mono, stereo, virtual surround sound
Frequency 53.267 kHz (NTSC), 52.781 kHz (PAL) 32 kHz
Sound channels Total channels 11 channels (hardware),
12-14 channels (software mixing) 		8 channels
Synthesis channels 11 channels
(6 FM synthesis, 1 LFO, 3 square waves, 1 noise) 		N/A
PCM sample channels 1 channel (hardware), 2-4 channels (software mixing) 8 channels
PCM sampling
capabilities 		File formats PCM, DPCM, ADPCM, VGM, XGM, TFM, WAV, MOD PCM, ADPCM, BRR[37]
Maximum sample
depth 		8-bit 16-bit
Maximum sample rate 32 kHz 32 kHz
Maximum bitrate 1024 Kbps (11% bandwidth usage) 1024 Kbps (99% bandwidth usage)[21]

Notes

  1. ↑ [16-bit data bus, 7.670453 MHz (NTSC), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte 16-bit data bus, 7.670453 MHz (NTSC), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte]
  2. ↑ [8-bit data bus, 2.684658 MHz (NTSC), 1 cycle per byte 8-bit data bus, 2.684658 MHz (NTSC), 1 cycle per byte]
  3. ↑ [16-bit data bus, 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte 16-bit data bus, 7.600489 MHz (PAL), 4 cycles per word, 16-bit (2 bytes) per word, 2 cycles per byte]
  4. ↑ [8-bit data bus, 2.660171 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.660171 MHz (PAL), 1 cycle per byte]
  5. ↑ [8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte 8-bit data bus, 2.684658–3.579545 MHz (NTSC), 2.660171–3.546895 MHz (PAL), 1 cycle per byte]
  6. ↑ [12 cycles per add[12] 12 cycles per add[12]]
  7. ↑ [6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)[13][14] 6 cycles per add: 17 cycles per 3 adds (2 cycles LDA, 6 cycles CLC, 6 cycles ADC, 3 cycles STA)[13][14]]
  8. ↑ [70 cycles per multiply[12] 70 cycles per multiply[12]]
  9. ↑ [55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)[15][14] 55 cycles per 16×8 multiply (3 cycles SEP, 6 cycles STA, 3 cycles STY, 12 cycles NOP, 2 cycles LDA, 4 cycles LDY, 6 cycles XBA, 2 cycles TYA, 2 cycles CLC, 2 cycles ADC, 2 cycles BCC, 2 cycles INY, 3 cycles REP, 6 cycles RTS)[15][14]]
  10. ↑ [110 cycles per 16×16 multiply (2x 16×8 multiplies) 110 cycles per 16×16 multiply (2x 16×8 multiplies)]
  11. ↑ [38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)[15][14] 38 cycles per Mode 7 multiply (3 cycles SEP, 7 cycles STA, 3 cycles XBA, 6 cycles STA, 6 cycles STY, 3 cycles REP, 2 cycles LDA, 2 cycles LDY, 6 cycles RTS)[15][14]]
  12. ↑ [140 cycles per divide[12] 140 cycles per divide[12]]
  13. ↑ [70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)[16][14] 70 cycles per divide (3 cycles STZ, 2 cycles LDY, 2 cycles ASL, 2 cycles BCS, 2 cycles INY, 2 cycles CPY, 4 cycles BNE, 7 cycles ROR, 3 cycles PHA, 2 cycles TXA, 2 cycles SEC, 7 cycles SBC, 4 cycles BCC, 2 cycles TAX, 7 cycles ROL, 4 cycles PLA, 7 cycles LSR, 2 cycles DEY, 6 cycles RTS)[16][14]]
  14. ↑ [SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)[17] SNES CPU geometry calculations: 13.32 kHz per polygon (80 adds, 111 multiplies, 9 divides)[17]]
  15. ↑ [Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),[17] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide[18] Super FX geometry calculations: 923 cycles per polygon (80 adds, 111 multiplies, 9 divides),[17] 1 cycle per add, 5 cycles per 16×16 multiply, 32 cycles per 16-bit divide[18]]
  16. ↑ [SNES CPU rendering:
    • Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,[29] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)[30][14]
    • Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
      • 13.32 kHz geometry per polygon
      • 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,[31] 2 cycles per CPY comparison),[14] 7 assignments (6 rasterization assignments,[31] 1 flat shading assignment),[32] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,[33] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)[34]
      • 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),[35] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup) SNES CPU rendering:
    • Framebuffer rendering: 256×160 framebuffer (double-buffered, 40 KB), 15 FPS (614.4 KB/s), 819.64 kHz framebuffer DMA (1.334 kHz per KB,[29] 30 cycles setup), 30 cycles per DMA setup (4 cycles LDX, 6 cycles STX, 8 cycles LDA, 12 cycles STA)[30][14]
    • Polygon rendering: 2.759905 MHz (15 FPS), 14.223 kHz per 8×8 pixel polygon
      • 13.32 kHz geometry per polygon
      • 361 Hz polygon rendering per polygon: 24 comparison cycles (12 comparisons,[31] 2 cycles per CPY comparison),[14] 7 assignments (6 rasterization assignments,[31] 1 flat shading assignment),[32] 220 multiply cycles (2 multiplies), 24 add cycles (4 adds), 5 broadcasts,[33] 110 cycles DMA access (40 bytes per polygon, 2 cycles per byte, 30 cycles setup)[34]
      • 542 Hz pixel rendering per 8×8 pixel polygon: 384 add cycles (1 add per pixel),[35] 158 cycles DMA (1 byte per pixel, 2 cycles per pixel, 30 cycles setup)]
  17. ↑ [SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)
    • 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup
    • 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)[36] SNES CPU texture mapping: 18.746 kHz per 8×8 texel polygon (5.426 kHz texture mapping per 8×8 texel polygon)
    • 316 cycles DMA per 8×8 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 30 cycles setup
    • 5110 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 630 vertex divide cycles per polygon (9 divides per polygon), 4480 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)[36]]
  18. ↑ [Super FX rendering:
    • Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles
    • Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
      • Geometry per polygon: 923 Super FX cycles
      • Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)
      • Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles) Super FX rendering:
    • Framebuffer rendering: 256×192 framebuffer (double-buffered, 48 KB), 15 FPS (737.28 KB/s), 983.562 kHz CPU framebuffer DMA (1.334 kHz per KB, 30 cycles setup), 2.950686 MHz Super FX cycles
    • Polygon rendering: 7.787949 MHz (15 FPS) Super FX cycles available, 3.632 kHz per 8×8 pixel polygon
      • Geometry per polygon: 923 Super FX cycles
      • Polygon rendering per polygon: 1083 Super FX cycles (361 CPU cycles)
      • Pixel rendering per 8×8 pixel polygon: 1626 Super FX cycles (542 CPU cycles)]
  19. ↑ [Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)
    • 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture
    • 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel) Super FX texture mapping: 6.916 kHz per 8×8 texel polygon (3.284 kHz texture mapping per 8×8 texel polygon)
    • 948 Super FX cycles (316 CPU cycles) DMA per 8×8 texel texture
    • 2336 divide cycles per 8×8 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 2048 texel divide cycles per 8×8 texel polygon (64 divides, 1 divide per texel)]

References

  1. ↑ File:Blast Processing Commercial.mp4
  2. ↑ ["Damien McFerran Retroinspection: Mega-CD", Retro Gamer, issue 61 (2009), page 84 "Damien McFerran Retroinspection: Mega-CD", Retro Gamer, issue 61 (2009), page 84]
  3. ↑ The Man Responsible For Sega's Blast Processing (Nintendo Life)
  4. ↑ How Sega Built the Genesis: Masami Ishikawa Inteview (Polygon)
  5. ↑ Game Players, "Vol. 7 No. 5 May 1994" (US; 1994-0x-xx), page 10
  6. ↑ 6.0 6.1 Blast Processing 101
  7. ↑ 7.0 7.1 Sega Mega Drive/Technical specifications
  8. ↑ 8.0 8.1 Super Nintendo Entertainment System technical specifications
  9. ↑ 9.0 9.1 9.2 SNES hardware specifications
  10. ↑ 10.0 10.1 10.2 Sega Genesis vs Super Nintendo
  11. ↑ 11.0 11.1 Anomie's Register Doc
  12. ↑ 12.0 12.1 12.2 Standard Instruction Execution Times
  13. ↑ SNES Development: General Advice
  14. ↑ 14.0 14.1 14.2 14.3 14.4 14.5 SNES Development: 65816 Reference
  15. ↑ 15.0 15.1 Super NES Programming: Multiplication
  16. ↑ Programming the 65816 Including the 6502, 65C02, and 65802
  17. ↑ 17.0 17.1 Design of Digital Systems and Devices (pages 95-97)
  18. ↑ 18.0 18.1 18.2 18.3 18.4 Super NES Programming: Super FX tutorial
  19. ↑ Obsolete Microprocessors
  20. ↑ File:Zilog Z80 Programmer's Reference Manual.pdf, page 33
  21. ↑ 21.0 21.1 16-bit stereo 32 kHz streaming success
  22. ↑ File:Sega Service Manual - Genesis II - Mega Drive II (PAL) - 001 - June 1993.pdf
  23. ↑ File:GenesisTechnicalOverview.pdf
  24. ↑ 3D math engine (SGDK)
  25. ↑ Interview: Lee Actor (Sterling Software Programmer)
  26. ↑ Star Fox 3D Tech Demo on Sega Genesis
  27. ↑ Star Fox 3D Tech Demo on Sega Genesis: Version 2 Using DMA
  28. ↑ SNES Developer Manual (Nintendo)
  29. ↑ SNES Development: DMA & HDMA
  30. ↑ SNES Development: Grog's Guide to DMA and HDMA on the SNES
  31. ↑ 31.0 31.1 Algorithms for Parallel Polygon Rendering (pages 33-34)
  32. ↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
  33. ↑ Algorithms for Parallel Polygon Rendering (page 36)
  34. ↑ Computer Organization and Design: The Hardware/Software Interface (page C-44)
  35. ↑ Algorithms for Parallel Polygon Rendering (page 35)
  36. ↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)
  37. ↑ Bit Rate Reduction (BRR)

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