Difference between revisions of "Mega Drive cartridges"
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* [[Cartridge]] memory: 512–8224 KB | * [[Cartridge]] memory: 512–8224 KB | ||
| − | + | :* [[ROM]]: 512 KB (4 [[Bit|Mbits]]) to 8 MB (64 Mbits){{ref|[http://www.eurogamer.net/articles/2012-11-09-2010s-sega-mega-drive-rpg-pier-solar-coming-to-xbox-360-pc-and-mac-in-hd 2010's Sega Mega Drive RPG Pier Solar coming to Xbox 360, PC and Mac in HD], [[wikipedia:Eurogamer|Eurogamer]]}}{{intref|SSFII Genesis Technical Information (2000-07-26)}} | |
| − | + | :* [[SRAM]]: 8 KB to 32 KB{{intref|MegaDrive/Genesis Pinouts}}{{ref|[http://www.second-dimension.com/docs/DXS-GEN24STH-01.pdf Second Dimension R&T DxS-GEN24STH-01]}} | |
* Cartridge ROM chips: 16‑bit{{ref|[http://www.smspower.org/Development/ROMPartNumbers ROM Part Numbers]}} | * Cartridge ROM chips: 16‑bit{{ref|[http://www.smspower.org/Development/ROMPartNumbers ROM Part Numbers]}} | ||
| − | + | :* Most cartridges: [[wikipedia:Mask ROM|MROM]], 5 MHz, 200 ns cycles{{fileref|MB834200A datasheet.pdf}}{{fileref|MB838200B datasheet.pdf}}{{ref|1=[https://youtu.be/yGzgKCsrNHM?t=6m7s Ben Heck’s 16-Bit Console Wars! (6:07)] (''[[wikipedia:Benjamin Heckendorn|The Ben Heck Show]]'')}} | |
| − | + | :* Some cartridges: MROM/[[EPROM]], 7.670453 MHz (NTSC), 7.600489 MHz (PAL), 130–131 ns cycles{{fileref|MB838200B datasheet.pdf}}{{ref|[http://www.second-dimension.com/docs/DXS-GEN24STH-01.pdf Second Dimension R&T DxS-GEN24STH-01]}}{{fileref|M27C322 datasheet.pdf}} | |
* Cartridge ROM bandwidth: 10 MB/s (most cartridges), 15.200978–15.340906 MB/s (some cartridges) | * Cartridge ROM bandwidth: 10 MB/s (most cartridges), 15.200978–15.340906 MB/s (some cartridges) | ||
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* GPU: [[Sega]] 315-5750{{intref|SVP Reference Guide (2008-02-06)}} ([[Samsung]] SSP1601) [[wikipedia:Digital signal processor|DSP]]{{intref|SVP documentation (2014-09-23)}}{{fileref|SSP1601 datasheet.pdf}} @ 23.01136 MHz{{intref|SVP Reference Guide (2008-02-06)}} (25 MIPS){{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}}{{fileref|SSP1601 datasheet.pdf}} | * GPU: [[Sega]] 315-5750{{intref|SVP Reference Guide (2008-02-06)}} ([[Samsung]] SSP1601) [[wikipedia:Digital signal processor|DSP]]{{intref|SVP documentation (2014-09-23)}}{{fileref|SSP1601 datasheet.pdf}} @ 23.01136 MHz{{intref|SVP Reference Guide (2008-02-06)}} (25 MIPS){{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}}{{fileref|SSP1601 datasheet.pdf}} | ||
| − | + | :* DSP core: 16-bit fixed-point arithmetic, 32-bit output, 16-bit word size, 25 registers (8 general, 8 external, 8 pointer, 1 status) | |
| − | + | :* [[wikipedia:Arithmetic logic unit|ALU]]: 32-bit, status register | |
| − | + | :* Multiplier: 32-bit output, 16x16-bit pipelined multiplication | |
* DSP buses: 6 buses{{fileref|SSP1601 datasheet.pdf}} | * DSP buses: 6 buses{{fileref|SSP1601 datasheet.pdf}} | ||
| − | + | :* 32-bit internal data buses: Data (D) bus (16-bit), subsidiary (S) bus (16-bit) | |
| − | + | :* 16-bit program data bus: Program data (PD) bus | |
| − | + | :* 16-bit external data bus: External (EXT) bus | |
| − | + | :* 16-bit address bus: Program address (PA) bus | |
| − | + | :* 32-bit arithmetic bus: Multiplier (M) bus | |
* Audio: 2 [[wikipedia:Pulse-width modulation|PWM]] channels{{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}} | * Audio: 2 [[wikipedia:Pulse-width modulation|PWM]] channels{{ref|[http://www.sega-16.com/2006/03/segas-svp-chip-the-road-not-taken/ Sega's SVP Chip: The Road Not Taken]}} | ||
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* DSP performance: | * DSP performance: | ||
| − | + | :* [[wikipedia:Multiply–accumulate operation|MAC operations]]: 1 MAC (multiply-accumulate) per cycle,{{fileref|SSP1601 datasheet.pdf}} 23.01136 million MACs per second | |
| − | + | :* Fixed-point calculations: 2 calculations (multiply and add) per cycle,{{intref|SVP documentation (2014-09-23)}} 46.02272 million calculations (23.01136 million multiplies, 23.01136 million adds) per second | |
* Framebuffer: 320×192, double-buffered, 30 FPS, 60 KB (dual 30 KB) buffers in [[wikipedia:FPM DRAM|FPM DRAM]] (1.8432 MB/s, 1.8432 MHz DSP cycles), 30 KB buffer in Mega Drive [[VRAM]] (921.6 KB/s DMA transfer, equivalent to 2.7648 MHz DSP cycles), 4.608 MHz DSP cycles for framebuffer | * Framebuffer: 320×192, double-buffered, 30 FPS, 60 KB (dual 30 KB) buffers in [[wikipedia:FPM DRAM|FPM DRAM]] (1.8432 MB/s, 1.8432 MHz DSP cycles), 30 KB buffer in Mega Drive [[VRAM]] (921.6 KB/s DMA transfer, equivalent to 2.7648 MHz DSP cycles), 4.608 MHz DSP cycles for framebuffer | ||
| − | + | :* [[Fillrate]]: 18.181818 [[Pixel|MPixels/s]] (18.181818 MHz FPM DRAM){{ref|1=[http://tinyurl.com/ppdd95v Virtua Racing (Euro)]}}{{fileref|TC511664B datasheet.pdf}} | |
* 3D polygon [[wikipedia:Transform and lighting|T&L]] geometry: | * 3D polygon [[wikipedia:Transform and lighting|T&L]] geometry: | ||
| − | + | :* Geometry transformations: 60,000 polygons/sec{{ref|1=369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA95 ''Design of Digital Systems and Devices'' (pages 95-97)]}} 32 cycles per divide|group=n}} | |
| − | + | :* Lighting calculations: 50,000 polygons/sec{{ref|1=390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),{{ref|1=[https://books.google.co.uk/books?id=iAvHt5RCHbMC&pg=PA95 ''Design of Digital Systems and Devices'' (pages 95-97)]}} 32 cycles per divide|group=n}} | |
* 3D polygon rendering: | * 3D polygon rendering: | ||
| − | + | :* Flat shading:{{ref|18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,{{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA33 ''Algorithms for Parallel Polygon Rendering'' (pages 33-36)]}}{{ref|1=[http://sirkan.iit.bme.hu/~szirmay/abbas.pdf#page=53 Transformation Of Rendering Algorithms For Hardware Implementation (page 53)]}}{{intref|SVP Reference Guide (2008-02-06)}} 2 framebuffer access cycles), 2 cycles per pixel{{ref|1=[https://books.google.co.uk/books?id=yiVRHrxFj2wC&pg=PA35 ''Algorithms for Parallel Polygon Rendering'' (page 35)]}}|group=n}} 20,000 polygons/sec (8×16 polygons),{{ref|724 cycles per polygon{{intref|SVP Register Guide (2008-02-06)}}|group=n}} 10,000 polygons/sec (16×32 polygons),{{ref|1492 cycles per polygon{{intref|SVP Register Guide (2008-02-06)}}|group=n}} 9000 polygons/sec (''[[Virtua Racing]]''){{ref|[http://www.ign.com/games/virtua-racing/gen-6398 Virtua Racing] ([[wikipedia:IGN|IGN]])}} | |
| − | + | :* Texture mapping: 3000 polygons/sec (8×16 texel textures){{ref|1=5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon) | |
*258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access | *258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access | ||
*4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel){{ref|1=[https://books.google.co.uk/books?id=teMHqC2BnuYC&pg=PA110 ''State of the Art in Computer Graphics: Visualization and Modeling'' (page 110)]}}|group=n}} | *4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel){{ref|1=[https://books.google.co.uk/books?id=teMHqC2BnuYC&pg=PA110 ''State of the Art in Computer Graphics: Visualization and Modeling'' (page 110)]}}|group=n}} | ||
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* Memory: 2179 KB (2.128 MB){{intref|SVP documentation (2014-09-23)}} | * Memory: 2179 KB (2.128 MB){{intref|SVP documentation (2014-09-23)}} | ||
| − | + | :* RAM: 131 KB | |
| − | + | ::* 128 KB [[wikipedia:FPM DRAM|FPM DRAM]] | |
| − | + | ::* 1 KB [[SRAM]] cache{{fileref|SSP1601 datasheet.pdf}} | |
| − | + | ::* 2 KB IRAM (instruction RAM) [[wikipedia:Cache (computing)|cache]]{{intref|SVP Reference Guide (2008-02-06)}} | |
| − | + | :* ROM: 2 MB (128 KB code, 1920 KB data){{intref|SVP Reference Guide (2008-02-06)}} | |
* RAM bandwidth: | * RAM bandwidth: | ||
| − | + | :* FPM DRAM: 34.679066 MB/sec (16-bit, 18.181818 MHz, 55ns cycles, 80ns access){{ref|1=[http://tinyurl.com/ppdd95v Virtua Racing (Euro)]}}{{fileref|TC511664B datasheet.pdf}} | |
| − | + | :* SRAM cache: 92.04544 MB/sec (32-bit, dual 16-bit banks,{{fileref|SSP1601 datasheet.pdf}}{{intref|SVP Register Guide (2008-02-06)}} 23.01136 MHz, 43ns){{intref|SVP documentation (2014-09-23)}}{{fileref|SSP1601 datasheet.pdf}} | |
}} | }} | ||
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{{MegaDrive}} | {{MegaDrive}} | ||
| − | [[Category:Sega Mega Drive]] | + | [[Category:Sega Mega Drive|Cartridges]] |
| + | [[Category:Mega Drive hardware|Cartridges]] | ||
Revision as of 23:38, 16 October 2018
Mega Drive cartridges are the primary storage medium for the Sega Mega Drive.
Contents
Design
The Mega Drive runs games housed in plastic cartridges uniquely shaped to fit the system. Though the technology exists within the console to run Sega Master System games, the Power Base Converter is required to convert between the differing pin connections and slot sizes.
Official Mega Drive cartridges are smaller than their Master System/Mark III counterparts, with rounded edges and bigger labels layered over the top and front of the cartridge.
As with the Master System, Sega-manufactured Japanese, Korean and Asian cartridges are shaped differently to those seen in North America, South America, Europe and Oceania, however the differences largely concern the aesthetics - "Eastern" Japanese-style cartridges opting for a more rounded approach with ridges, while "Western" cartridges being more angular and simplistic. Unlike the Master System, the Mega Drive has end-labels for easier reading and storage in Western regions.
Pin layout is the same between the two types, however the base of the cartridge determines whether it can be safely inserted into the system - two extra pieces of plastic prevent Japanese cartridges from being inserted in western systems - these can be removed with modification, or as mentioned above, circumvented with adapters. This extra plastic is not present in systems such as the Genesis 3 and Sega 32X, nor does it exist in Japanese Mega Drives.
One interesting feature of Japanese cartridges is a inclusion of a cartridge "lock", which prevents the cartridge from being removed when the system turns on. A plastic piece from the system is slid across to a gap on the left hand side of a Japanese cartridge, securing it in place when the power switch is moved (similar tricks can be found on the Super NES and the TurboGrafx-16). This locking mechanism is only present in Japanese Model 1 Mega Drives and is absent in all western models - the vast majority of Western cartridges lack the gap required for cartridge locking, with exceptions being the likes of "special" cartridges, e.g. Sonic & Knuckles.
The lack of cartridge lock can be exploited, for example, to gain access to the level selection screen in Sonic 3D Blast.
Official cartridge designs
North American
European
Japanese
Brazillian
South Korean
Cartridge designs for Altered Beast - though labels would change dramatically over the console's run, the physical shape would remain consistent.
Alternative cartridge designs
Though Sega manufactured the bulk of Mega Drive cartridges, many were created externally by the likes of Electronic Arts, Accolade, Sunsoft and Codemasters.
Accolade/Ballistic used due to an initial unwillingness to seek an official license from Sega. (Double Dragon).
Codemasters. The company would take things a step further with the introduction of the J-Cart. (Brian Lara Cricket).
Electronic Arts, with the infamous (and useless) coloured tab on the left hand side. (Shaq Fu).
Technical information
- Cartridge memory: 512–8224 KB
- Cartridge ROM chips: 16‑bit[5]
- Cartridge ROM bandwidth: 10 MB/s (most cartridges), 15.200978–15.340906 MB/s (some cartridges)
Special cases
Sonic & Knuckles
Sonic & Knuckles famously introduced so-called "lock-on" technology to the Mega Drive library, in which a second cartridge could be stacked on top to create a new game. While there were rumours of other lock-on games in development, Sonic & Knuckles is the only example which made it to market.
While the vast majority of games will communicate with Sonic & Knuckles, the end result will be a randomised variant of Blue Sphere. To access Blue Sphere in full, Sonic the Hedgehog must be "locked-on", and Knuckles the Echidna in Sonic the Hedgehog 2 and Sonic the Hedgehog 3 & Knuckles can be accessed by locking on Sonic the Hedgehog 2 and Sonic the Hedgehog 3, respectively.
If a cartridge with a more than 2MB of storage is locked on to the cartridge, Blue Sphere will not load, and the setup will revert to the standard Sonic & Knuckles game. This is due to a quirk in how the game reads data from its locked-on segment - rather than reading from the first 2MB of the locked-on ROM, it will read from the last 2MB and subsequently not detect a correct header. Sonic Classics is the only exception to this rule - a compilation seemingly designed so that data from the original Sonic the Hedgehog would be detected in the right place for Blue Sphere to load.
While Sonic the Hedgehog 3 is a region-locked game, Sonic & Knuckles is not, nor does it care what region Sonic 3 is from. As such, the subsequent creation of Sonic the Hedgehog 3 & Knuckles will also be region free.
J-Cart
Created by Codemasters, J-Carts break the norm by including two extra joystick ports built into the cartridge. This permitted four-way gameplay without a multitap adapter. Only six J-Carts were released: Pete Sampras Tennis, Pete Sampras Tennis 96, Micro Machines 2, Micro Machines 96, Micro Machines Military Edition, and Super Skidmarks. Several were also released as standard cartridges.
Sega Virtua Processor
Virtua Racing contains a custom-designed DSP chip, known officially as SVP, or Sega Virtua Processor. It allows for enhanced graphics and sound capabilities. This chip essentially serves as an extra processor, allowing the game to produce a significantly higher number of polygons than would be possible on a standard Mega Drive. It was also significantly more powerful than the Super Nintendo's Super FX chip. However, Virtua Racing released with a more expensive retail price.
The SVP chip was revealed for the Mega Drive in Summer 1993, before the Mega Drive version of Virtua Racing released in 1994.[10] Interestingly, Virtua Racing was the first to showcase the power of the SVP chip - plans were underway to produce more games using this chip, using a "Modular Converter" cartridge to cut production costs. This converter would contain the SVP chip, with the enhanced game designed to use the SVP chip plugging into the top of the unit.[11] However, due to the costs of production against the Mega Drive/Genesis' age and falling popularity, the project was dropped. Virtua Racing also has a cartridge roughly one-and-a-half times the size of a usual Mega Drive cartridge due to the added chip, and is incompatible with the Sega 32X add-on.
Technical specifications
- See Sega Mega Drive technical specifications for standard Mega Drive hardware specifications
- See also Blast processing for SuperFX comparison
The SVP chip adds the following capabilities to the Mega Drive hardware.
- DSP core: 16-bit fixed-point arithmetic, 32-bit output, 16-bit word size, 25 registers (8 general, 8 external, 8 pointer, 1 status)
- ALU: 32-bit, status register
- Multiplier: 32-bit output, 16x16-bit pipelined multiplication
- DSP buses: 6 buses[14]
- 32-bit internal data buses: Data (D) bus (16-bit), subsidiary (S) bus (16-bit)
- 16-bit program data bus: Program data (PD) bus
- 16-bit external data bus: External (EXT) bus
- 16-bit address bus: Program address (PA) bus
- 32-bit arithmetic bus: Multiplier (M) bus
Graphics
- DSP performance:
- MAC operations: 1 MAC (multiply-accumulate) per cycle,[14] 23.01136 million MACs per second
- Fixed-point calculations: 2 calculations (multiply and add) per cycle,[13] 46.02272 million calculations (23.01136 million multiplies, 23.01136 million adds) per second
- Framebuffer: 320×192, double-buffered, 30 FPS, 60 KB (dual 30 KB) buffers in FPM DRAM (1.8432 MB/s, 1.8432 MHz DSP cycles), 30 KB buffer in Mega Drive VRAM (921.6 KB/s DMA transfer, equivalent to 2.7648 MHz DSP cycles), 4.608 MHz DSP cycles for framebuffer
- 3D polygon T&L geometry:
- 3D polygon rendering:
Memory
Notes
- ↑ [369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),[18] 32 cycles per divide 369 cycles per polygon (81 multiplies/polygon, 9 divides/polygon),[18] 32 cycles per divide]
- ↑ [390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),[18] 32 cycles per divide 390 cycles per polygon (102 multiplies/polygon, 9 divides/polygon),[18] 32 cycles per divide]
- ↑ [18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,[19][20][12] 2 framebuffer access cycles), 2 cycles per pixel[21] 18.40336 MHz available (4.608 MHz for framebuffer), 468 cycles per polygon (390 T&L cycles, 42 DRAM cycles for 40 bytes, 34 raster cycles,[19][20][12] 2 framebuffer access cycles), 2 cycles per pixel[21]]
- ↑ [724 cycles per polygon[22] 724 cycles per polygon[22]]
- ↑ [1492 cycles per polygon[22] 1492 cycles per polygon[22]]
- ↑ [5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon)
- 258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access
- 4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel)[24] 5366 cycles per 8×16 texel polygon (4642 cycles texture mapping per 8×16 texel polygon)
- 258 cycles per 8×16 texel texture: 2 block moves, 2 cycles per texel (1 byte per texel), 2 cycles access
- 4384 divide cycles per 8×16 texel polygon: 73 divides per 8×8 texel polygon, 288 vertex divide cycles per polygon (9 divides per polygon), 4096 texel divide cycles per 8×16 texel polygon (128 divides, 1 divide per texel)[24]]
Bank switching
The Mega Drive can only address up to 4MB of game at any one time, meaning under normal circumstances, Mega Drive games are limited to a maximum size of 4MB (or 32 megabits as was more commonly advertised). This is increased, however, using a technique known as bank switching - hardware built into the cartridge which allows "banks" of memory to be "switched" at run time. As an example, the first half of a game might be loaded into memory when the console is turned on, and when a certain condition is met, the second half is loaded in, replacing the first half (how this is achieved depends on how the game is programmed).
Bank switching in dedicated video game consoles dates back to at least the Atari 2600, however it was not implemented in Mega Drive titles until the mid-1990s, as for the most part, cartridge space was not considered an issue for developers (or at least, not enough of one to justify the extra cost implementing a bankswitching system, and for many years the Sega Mega-CD was a viable option too).
List of games
- Super Street Fighter II: The New Challengers (1994; 5MB/40Mb)
- Pier Solar and the Great Architects (2010; 8MB/64Mb)
- Paprium (2018; 10MB/80Mb)
References
- ↑ 2010's Sega Mega Drive RPG Pier Solar coming to Xbox 360, PC and Mac in HD, Eurogamer
- ↑ SSFII Genesis Technical Information (2000-07-26)
- ↑ MegaDrive/Genesis Pinouts
- ↑ 4.0 4.1 Second Dimension R&T DxS-GEN24STH-01
- ↑ ROM Part Numbers
- ↑ File:MB834200A datasheet.pdf
- ↑ 7.0 7.1 File:MB838200B datasheet.pdf
- ↑ Ben Heck’s 16-Bit Console Wars! (6:07) (The Ben Heck Show)
- ↑ File:M27C322 datasheet.pdf
- ↑ File:CVG UK 150.pdf, page 50
- ↑ File:GamePro US 057.pdf, page 160
- ↑ 12.0 12.1 12.2 12.3 12.4 SVP Reference Guide (2008-02-06)
- ↑ 13.0 13.1 13.2 13.3 SVP documentation (2014-09-23)
- ↑ 14.0 14.1 14.2 14.3 14.4 14.5 14.6 File:SSP1601 datasheet.pdf
- ↑ 15.0 15.1 Sega's SVP Chip: The Road Not Taken
- ↑ 16.0 16.1 Virtua Racing (Euro)
- ↑ 17.0 17.1 File:TC511664B datasheet.pdf
- ↑ 18.0 18.1 Design of Digital Systems and Devices (pages 95-97)
- ↑ Algorithms for Parallel Polygon Rendering (pages 33-36)
- ↑ Transformation Of Rendering Algorithms For Hardware Implementation (page 53)
- ↑ Algorithms for Parallel Polygon Rendering (page 35)
- ↑ 22.0 22.1 22.2 SVP Register Guide (2008-02-06)
- ↑ Virtua Racing (IGN)
- ↑ State of the Art in Computer Graphics: Visualization and Modeling (page 110)