Difference between revisions of "Sega NAOMI"

Revision as of 04:54, 2 December 2016

Sega NAOMI

Manufacturer: Sega

Variants: Sega NAOMI GD-ROM, Sega NAOMI Multiboard, Sega Dreamcast, Atomiswave, Sega Aurora

Add-ons: GD-ROM

Release	Date	RRP	Code

The NAOMI (New Arcade Operation Machine Idea) is an arcade system released by Sega in 1998. It was designed as a successor to Sega Model 3 hardware, using a similar architecture to the Sega Dreamcast.

The NAOMI was succeeded by the Sega Hikaru and Sega NAOMI 2 boards, though having out-lasted the NAOMI 2, Hikaru and Sega Aurora. The Sega Chihiro, or possibly even the Sega Lindbergh, could also be seen as successors.

History

The NAOMI debuted at a time when traditional arcades were on a decline, and so was engineered to be a mass-produced, cost-effective machine reliant on large game ROM cartridges which could be interchanged by the arcade operator. This is contrary to systems such as the Model 3, in which each board, despite sharing largely the same specifications, would be bespoke, with the built-in ROMs being flashed with games during the manufacturing process. This is not the first time such an idea was utilised by Sega, but never before had technology been used for a cutting-edge Sega arcade specification.

Unlike most hardware platforms in the arcade industry, NAOMI was widely licensed for use by other manufacturers, many of which were former rivals to Sega, such as Taito, Capcom and Namco. It is also one of the longest-serving arcade boards, being supported from 1998 to 2009. It is a platform where many top-rated Sega franchises were born, including Virtua Tennis, Samba de Amigo, Crazy Taxi and Monkey Ball.

Hardware

The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same Hitachi SH-4 CPU and Yamaha AICA based sound system, along with different revisions of the PowerVR Series 2 GPU architecture. While the CPU of the NAOMI and Dreamcast operate at the same clock frequency, the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a faster PowerVR2 graphics processor, faster VRAM bandwidth,^{[n 1]} and FPGA processors with additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance, or for a multi-monitor setup.

After The House of the Dead 2, a newer revision of the PowerVR2 graphics chip was used in subsequent NAOMI systems.^[1] According to VideoLogic's president and CEO, Hossein Yassaie, in September 1998: "With Dreamcast, PowerVR set out to create a new standard in 3D graphics for console gaming; now with Sega’s Naomi, we will deliver unprecedented levels of 3D performance to arcade systems".^[3]

Another key difference between NAOMI and Dreamcast lies in the game-media - the NAOMI primarily uses ROM PC (printed circuit) boards (i.e. large game cartridges) with up to 168 MB of usable data (more expensive but with faster loading), while the Dreamcast uses GD-ROM optical-storage with up to 1GB of storage (at the expense of load times). The NAOMI was extended in 1999 so that it could interface with GD-ROM-based arcade games. This system uses standard PC SDR-DIMM modules which are battery backed-up for storing game data. The game data is read from the GD-ROM at bootup, stored onto the SDR RAM to which the NAOMI reads from during game. This leaves less wear on the GD-ROM drive as it's only used when the memory is empty or corrupted, else it will use the SDR RAM for boot-up every subsequent power on after checking the data integrity. If the battery fails, the system is left turned off for several days or the game GD-ROM is changed, the game will be reloaded from the GD-ROM drive.

Along with the standard version, three more variants also exist:

First Edition — The initial release of NAOMI hardware was housed in an aluminium shell, similar in design to some versions of the earlier Model 2 and Model 3 system hardware. This version is known to be used in House of the Dead 2 arcade machines, with the game ROM board pre-installed inside the case. It is unknown whether this is a unique hardware variant specifically for House of the Dead 2, or whether it is compatible with later NAOMI releases. This prototype uses an earlier revision of the PowerVR2 graphics processor.^[1]
Multiboard — Several NAOMI motherboards joined onto a single board which connects the multiple boards together to created a more powerful parallel processing system.
Satellite Terminal — independent NAOMI cabinets connected to a master one

NAOMI boards can be used in special game cabinets (NAOMI Universal Cabinet) where a theoretical maximum of sixteen boards can be used in a parallel processing format.

The NAOMI multiboard setup uses a different BIOS chip than a regular NAOMI to handle all the boards but the whole system only uses one copy of the game cartridge, of which only four games were released.

Technical Specifications

NAOMI Specifications

See Sega Dreamcast technical specifications for more details on the capabilities of the general Dreamcast/Naomi hardware architecture, though the specifications for the Naomi differ from the Dreamcast in various ways, as listed below.^[1]

Board composition: Motherboard, Internal ROM Board, Filter Board
- 1999 revision: Motherboard, Internal ROM Board, Filter Board, I/O Board
Operating systems:
- Sega native operating system
- Custom Windows CE, with DirectX 6.0, Direct3D and OpenGL support

Main

Main CPU: Hitachi SH-4 @ 200 MHz^[4]^[5]
- Units: 128‑bit SIMD vector unit with graphic functions, 64‑bit floating‑point unit, 32‑bit fixed‑point unit
- Bus width: 128‑bit internal, 64‑bit external
- Bandwidth: 3.2 GB/s internal, 1.6 GB/s external
- Fixed‑point performance: 360 MIPS^{[n 2]}
- Floating‑point performance: 1.4 GFLOPS^{[n 3]}
MCU:
- Main MCU: Sega Custom Z80 @ 21.333 MHz (8/16‑bit instructions @ 3.093 MIPS)^[6]
- I/O Board MCU: Toshiba TMP90PH44 @ 14.745 MHz (8‑bit instructions @ 3.68625 MIPS)^[7]
- Optional cartridge MCU: Microchip PIC12C508A/PIC16C621A @ 4/40 MHz (8‑bit RISC instructions @ 1/5 MIPS)^[8]^[9]
FPGA: 2× FPGA^[1]
- Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz^[10]
- Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6&nbsp^[11]

Graphics

GPU: 2 core processors (SH‑4 SIMD, PowerVR2)
- Cores: 6 cores (SH‑4 SIMD, 5 PowerVR2 cores)
GPU geometry processor: Hitachi SH-4 SIMD @ 200 MHz
GPU rasterizer: NEC-VideoLogic PowerVR2 @ 100 MHz^[12]
- Revision: Newer revision of PowerVR2 used in NAOMI systems (after The House of the Dead 2),^[12] rendering performance doubled^{[n 4]}
- Cores: TA (Tile Accelerator), 2x ISP (Image Synthesis Processors), TSP (Texture & Shading Processor), Triangle Setup FPU, RAMDAC
  - Units: 88 rendering units (74 ISP units, 10 TSP units, 3 FPU units, 1 RAMDAC)
- ISP units: 2x ISP Precalc Units, 2x ISP PE Arrays (64 PE processor elements), 2x Depth Accumulation Buffers, 2x Span RLC, 2x Span Sorters, 2x ISP Parameter Cache
- TSP units: TSP Precalc, Parameter Cache, Texture Cache, Iterator Array, Pixel Processing Engine, Tile Accumulation Buffer, Secondary Accumulation Buffer, Combine & Bump Map Unit, Fog Unit, Alpha Blending Unit^[16]
- Triangle Setup FPU: 3 FPU rendering units, 1 GFLOPS
  - 2x ISP Setup FPU: 100 MHz, 728 MFLOPS, surface and culling processing for polygons, 14,285,714 polygons/sec^{[n 5]}
  - TSP Setup FPU: 100 MHz, 364 MFLOPS, shading and texture processing^[17] for tiles processed by ISP^[14]
- RAMDAC: 230 MHz
- Buses: 2 buses at 125 MHz, 64-bit TA Bus for transferring polygons and textures (1 GB/s), 32-bit PVRIF Bus for register memory (500 MB/s)
- Features: Bump mapping, fog, alpha blending, mipmapping, anti-aliasing, environment mapping, specular effects,^[4] normal mapping, tiled rendering, deferred rendering, back‑face culling, hidden surface removal. See Sega Dreamcast Technical Specifications for more details on PowerVR2 graphics system.
DAC: Sega 315‑6145 (Rohm BU1426KS) @ 35.4695 MHz^[19]
- Bus width: 24‑bit
Display resolution: 320×240 to 800×608 pixels, progressive scan, JAMMA/VGA
- Internal resolution: 320×240 to 1600×1200 pixels
Color depth: 16-bit RGB to 32‑bit ARGB, 65,536 to 16,777,216 colors (24‑bit color) with 8‑bit (256 levels) alpha blending, YUV and RGB color space, color key overlay
Framebuffer:
- Full framebuffer: 320×240×16‑bit (150 KB) to 1600×1200×24‑bit (5625 KB)
- Strip/Tile buffer: 32×32×16‑bit (4 KB) to 32×32×24‑bit (8 KB)^[20]
VRAM: 16 MB (effectively up to 42–127 MB with texture compression)
- Framebuffer: 300–5625 KB (optional), average 1200–1800 KB (640×480, 16/24-bit color, double-buffered)
- Polygons: Stored in double-buffered display lists,^[21]^[22] 22 bytes per shaded triangle,^{[n 6]} 31 bytes per textured triangle,^{[n 7]} 36 bytes per bump-mapped triangle,^{[n 8]} 38 bytes per volume-modified triangle,^{[n 9]} 96 bytes per sprite^{[n 10]}^[23]
- Textures: 32 KB^{[n 11]} to 16 MB (effectively 42–127 MB with texture compression), average 5–10 MB (effectively 40–60 MB with texture compression), 32 bytes^{[n 12]} to 386 KB^{[n 13]}^[24] or 1026 KB^{[n 14]} per texture^[25]
- VRAM bandwidth: 1 GB/s (effectively up to 3–7 GB/s with texture compression)
- Note: Main RAM also used to store polygon display lists. Textures transferred directly to VRAM. Textures can be streamed directly from high-speed ROM cartridge.^[26] Main RAM can also optionally be used to store textures.
Floating-point performance: 2.4 GFLOPS
- SH-4 SIMD: 1.4 GFLOPS geometry
- PowerVR2: 1 GFLOPS rendering
Geometry pipeline: SH‑4 SIMD
- Geometry bandwidth: 3.2 GB/s
- Floating‑point performance: 1.4 GFLOPS
Rendering fillrate:
- 6 GPixels/s: Maximum fillrate for opaque polygons^{[n 15]}
- 1 GPixel/s: Average fillrate for translucent and opaque polygons^[3]^{[n 16]}
- 200 MPixels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60^{[n 17]}
Texture fillrate:^{[n 18]}
- 6 GTexels/s: Maximum fillrate for opaque polygons
- 1 GTexel/s: Average fillrate for translucent and opaque polygons
- 200 MTexels/s: Minimum fillrate for translucent polygons with hardware sort depth of 60
SH-4 Polygon T&L Geometry: 1.4 GFLOPS
- Matrix transformations: 50 million vertices/s
- Perspective transformations: 16.6 million vertices/sec, 16 million polygons/s
- 1 light source: 14.2 million vertices/s, 14 million polygons/s
- 4 light sources: 6.89 million vertices/s, 6.8 million polygons/s
CLX2 polygon rendering: Front‑facing polygons drawn on screen, not including overdrawn and back‑facing polygons
- 16 million vertices/s^{[n 19]}
- 14 million polygons/s: Lighting, flat shading^{[n 20]}
- 12 million polygons/s: Lighting, texture mapping^{[n 21]}
- 10 million polygons/s: Lighting, texture mapping, shadows, modifier volumes^{[n 22]}
- 8.3 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping^{[n 23]}
- 8.2 million polygons/s: Lighting, texture mapping, anisotropic filtering^{[n 24]}
2D sprite capabilities: Sprites rendered as textured translucent quad polygons
- Colors per sprite: 16 colors (4-bit color) to 16,777,216 colors (24-bit color)
- Sprite sizes: 8×8 texels (224 bytes) to 1024×1024 texels (386.2 KB)
- Sprite fillrate: 200 MTexels/s
- Maximum sprites per frame: 52,083 sprites (8×8, 60 FPS)
- Maximum texels per scanline: 13,888 texels (60 FPS)
- Maximum sprites per scanline: 1736 sprites (60 FPS)

Sound

Sound engine: Yamaha AICA Super Intelligent Sound Processor @ 67 MHz
- Internal CPU: 32‑bit ARM7 RISC CPU @ 45 MHz
- CPU performance: 40 MIPS
- PCM/ADPCM: 16‑bit depth, 48 kHz sampling rate (DVD quality), 64 channels
- Other features: DSP, sound synthesizer

Memory

Overall memory: 92–506 MB
Internal processor cache: 120.076 KB^{[n 25]}^[20]
- SH4 CPU cache: 25.564 KB^{[n 26]}
- PowerVR2 GPU cache: 46 KB^{[n 27]}
- AICA audio cache: 32.011 KB^{[n 28]}
- I/O Board MCU: 16.5 KB^{[n 29]}
System RAM: 57,408 KB (56.0625 MB)
- Main RAM: 32 MB SDRAM
- VRAM: 16 MB SDRAM (unified framebuffer/polygon/texture memory)
- Sound RAM: 8 MB SDRAM
- SRAM: 64 KB
System ROM: 2048.125 KB (2 MB BIOS EPROM, 128 bytes EEPROM)
Cartridge ROM: 34–448 MB
- Sega 1998/1999 format: 34–184 MB (32–176 MB FlashROM/MROM, 0–4 MB EPROM)
- Namco 2000 format: 136–400 MB (136–256 MB FlashROM, 0–144 MB MROM)
- Sega 2005 format: 128–448 MB (128–448 MB FlashROM, 0–40 MB EPROM,^[31] 128 KB Flash PROM)^[32]
Cartridge RAM: 32–64 KB SRAM
Optional cartridge MCU memory: 793/1888 bytes (25/96 bytes SRAM, 768/1792 bytes EPROM)^[8]^[9]

Bandwidth

Internal processor cache bandwidth:
- SH4: 3.2 GB/s^{[n 30]}
- PowerVR2: 28 GB/s^{[n 31]}
- AICA: 256 MB/s^{[n 32]}
RAM/ROM memory bandwidth: 2.636–3.224 GB/s
System RAM bandwidth: 2 GB/s
- Main RAM: 800 MB/s^{[n 33]}
- VRAM: 1 GB/s^{[n 34]}
- Sound RAM: 132 MB/s^{[n 35]}
- SRAM: 44 MB/s^{[n 36]}
System ROM bandwidth: 24 MB/s
- EPROM: 20 MB/s^{[n 37]}
- EEPROM: 4 MB/s^{[n 38]}
Cartridge ROM bandwidth: 612 MB/s to 1.2 GB/s^{[n 39]}
- Sega 1998 format: 612 MB/s^{[n 40]}
- Sega 1999/2005 format: 900 MB/s^{[n 41]}
- Namco 2000 format: 1.2 GB/s^{[n 42]}
- Note: High-speed access allows ROM cartridge to effectively be used as RAM.^[26]
Cartridge RAM bandwidth: 28–100 MB/s^{[n 43]}

NAOMI GD-ROM Specifications

The NAOMI GD-ROM, released in 1999, is identical to the standard NAOMI, but uses GD-ROM discs for storage instead of ROM cartridges. It comes with a DIMM Board, which is very similar to a ROM cartridge, but with RAM instead of ROM. When a game is installed, the GD ROM content is loaded onto the DIMM Board RAM, so that the game data runs from the DIMM Board rather than the GD-ROM disc.

Board composition: Motherboard, Internal ROM Board, Filter Board, I/O Board, DIMM Board
Storage: GD-ROM disc drive @ 12× speed, 1 GB per GD-ROM disc
- GD-ROM transfer rate: 1800 KB/s

Memory

Overall memory: 66–570 MB
System RAM: 57,408 KB (56.0625 MB)
Internal processor cache: 110,286 bytes (107.701 KB)
System ROM: 2048.125 KB (2.0001 MB)
DIMM Board RAM: 8–512 MB DIMM SDRAM^[42]

Bandwidth

RAM bandwidth: 3 GB/s
- Main RAM: 800 MB/s
- VRAM: 1 GB/s
- Sound RAM: 132 MB/s
- SRAM: 44 MB/s
- DIMM RAM: 1.064–2.128 GB/s^{[n 44]}

NAOMI Multiboard Specifications

The NAOMI Multiboard, released in 1999, stacks together multiple NAOMI system boards for parallel processing in a single arcade system, ranging from 2 to 16 system boards. Since the 16‑board variant is not known to have been used by any games, the following specifications are for the 2‑board and 4‑board variants:

Board composition: 2–4 NAOMI system boards

Main

CPU: 2–4× Hitachi SH-4 @ 200 MHz
- Performance: 720–1440 MIPS, 2.8–5.6 GFLOPS
MCU: 2–4× Sega Custom Z80 @ 21.333 MHz (8‑bit & 16‑bit instructions @ 6–12 MIPS)
FPGA: 4–8× FPGA
- 2–4× Altera FLEX EPF8452AQC160‑3 FPGA @ 125 MHz
- 2–4× Sega 315‑6188 (Altera EPC1064PC8) FPGA Configuration Device @ 6 MHz

Graphics

GPU: 4–8 core processors (2–4 SH‑4 SIMD, 2–4 PowerVR2)
- Core units: 12–24 units (2–4 SH‑4 SIMD, 10–20 PowerVR2 cores)
Display resolution: 2–3 monitors, 640×240 to 2400×608, progressive scan, widescreen JAMMA/VGA
- Internal resolution: 640×240 to 1600×1200 pixels per board
Geometry pipeline:
- Geometry bandwidth: 6–12 GB/s (2–4 SH‑4 SIMD)
- Floating‑point performance: 2.8–5.6 GFLOPS (2–4 SH‑4 SIMD)
Rendering fillrate:
- 8–16 GPixels/s: Opaque polygons
- 2–4 GPixels/s: Translucent and opaque polygons
Texture fillrate: 2–4 GTexels/s
Floating-point performance: 3.0666–6.1332 GFLOPS
- SH-4 SIMD: 2.8–5.6 GFLOPS geometry
- PowerVR2: 266.6–533.2 MFLOPS rendering
SH-4 polygon T&L geometry:
- Matrix transformations: 100–200 million vertices/s
- Perspective transformations: 32–64 million polygons/s
- Lighting calculations: 28–56 million polygons/s
CLX2 polygon rendering:
- 32–64 million vertices/sec
- 19–38 million polygons/s: Lighting, flat shading
- 19–38 million polygons/s: Lighting, texture mapping, shadows, modifier volumes
- 16–32 million polygons/s: Lighting, texture mapping, Gouraud shading, shadows, modifier volumes, bump mapping
- 16–32 million polygons/s: Lighting, texture mapping, anisotropic filtering

Sound

Sound engine: 2–4× Yamaha AICA Super Intelligent Sound Processor @ 67 MHz
- Internal CPU: 2–4× 32‑bit ARM7 RISC CPU @ 45 MHz
- CPU performance: 80–160 MIPS
- PCM/ADPCM: 128–512 channels

Memory

System RAM: 112–224 MB
- Main RAM: 64–128 MB
- VRAM: 32–64 MB
- Sound RAM: 16–32 MB
- SRAM: 64–128 KB
Internal processor cache: 220,572–441,144 bytes (215.402–430.804 KB)
System ROM: 4096.25–8192.5 KB (4–8 MB BIOS EPROM, 256–512 bytes EEPROM)

Bandwidth

System RAM bandwidth: 4–8 GB/s
- Main RAM: 1.6–3.2 GB/s^{[n 45]}
- VRAM: 2–4 GB/s^{[n 45]}
- Sound RAM: 264–528 MB/s^{[n 46]}
- SRAM: 88–176 MB/s^{[n 46]}
Internal processor cache bandwidth:
- SH4: 3.2–6.4 GB/s^{[n 45]}
- PowerVR2: 41–83 GB/s
- AICA: 512–1024 MB/s^{[n 47]}
System ROM bandwidth: 48–96 MB/s
- EPROM: 40–80 MB/s^{[n 46]}
- EEPROM: 8–16 MB/s^{[n 46]}

Gallery

First Edition

Sockets, with open lid
Inside, internal ROM board removed
Model number
Outer case, back
Outer case, right
Outer case, left
Motherboard, top
Motherboard, bottom
Motherboard, side

Main version

Top of the motherboard
Bottom of the motherboard
Sockets
Full System
NAOMI Case
GD-ROM slot
DIMM Module + Key

List of Games

Promotional material

Press Kit (1998)

Notes

↑ [125 MHz,^[1]^[2] compared to the Dreamcast's 100 MHz 125 MHz,^[1]^[2] compared to the Dreamcast's 100 MHz]
↑ [2 instructions per cycle 2 instructions per cycle]
↑ [7 floating-point operations per cycle 7 floating-point operations per cycle]
↑ [Scaled for high-end arcade technology,^[13] with parallel ISP cores and increased PE processing elements within processor.^[14] NAOMI has average fillrate of 1 gigapixel/sec,^[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[15] Scaled for high-end arcade technology,^[13] with parallel ISP cores and increased PE processing elements within processor.^[14] NAOMI has average fillrate of 1 gigapixel/sec,^[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[15]]
↑ [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles^[17]^[18] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles^[17]^[18]]
↑ [Flat/Gouraud shading, 43 bytes double-buffered Flat/Gouraud shading, 43 bytes double-buffered]
↑ [Gouraud shading, 62 bytes double-buffered Gouraud shading, 62 bytes double-buffered]
↑ [Textured, Gouraud shading, bump mapping, 72 bytes double-buffered Textured, Gouraud shading, bump mapping, 72 bytes double-buffered]
↑ [Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered]
↑ [Sprite, quad, 192 bytes double-buffered Sprite, quad, 192 bytes double-buffered]
↑ [8×8 texture, 16 colors 8×8 texture, 16 colors]
↑ [8×8×4-bit 8×8×4-bit]
↑ [1024×1024×24-bit 1024×1024×24-bit]
↑ [2048×2048×16-bit 2048×2048×16-bit]
↑ [32 pixels/cycle per ISP,^[27] 1 pixel per PE (processor element),^[14]^[28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP^[29] 32 pixels/cycle per ISP,^[27] 1 pixel per PE (processor element),^[14]^[28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP^[29]] (Wayback Machine: 2000-08-23 20:47)
↑ [10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP 10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP]
↑ [60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP 60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP]
↑ [Same as pixel rendering fillrate Same as pixel rendering fillrate]
↑ [14 cycles per 3 vertices, per ISP FPU 14 cycles per 3 vertices, per ISP FPU]
↑ [14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon 14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon]
↑ [Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon]
↑ [Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon]
↑ [138,888 polygons per scene, 100–700 texels per polygon 138,888 polygons per scene, 100–700 texels per polygon]
↑ [137,664 polygons per scene,^[30] 100–700 texels per polygon 137,664 polygons per scene,^[30] 100–700 texels per polygon]
↑ [122,958 bytes 122,958 bytes]
↑ [26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers 26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers]
↑ [47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer 47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer]
↑ [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]
↑ [16,896 bytes: 512 bytes RAM, 16 KB ROM^[7] 16,896 bytes: 512 bytes RAM, 16 KB ROM^[7]]
↑ [128‑bit, 200 MHz 128‑bit, 200 MHz]
↑ [2304‑bit, 100 MHz: 32-bit TA tile buffer,^[33] 2x 32-bit ISP registers, 32-bit TSP registers,^[34] 2x 1024-bit ISP PE Arrays,^[14] 64-bit TSP Texture Cache,^[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer 2304‑bit, 100 MHz: 32-bit TA tile buffer,^[33] 2x 32-bit ISP registers, 32-bit TSP registers,^[34] 2x 1024-bit ISP PE Arrays,^[14] 64-bit TSP Texture Cache,^[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer]
↑ [32‑bit, 67 MHz 32‑bit, 67 MHz]
↑ [64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60^[35] 64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60^[35]]
↑ [64‑bit, 125 MHz, Hynix HY57V161610DTC‑8^[2] 64‑bit, 125 MHz, Hynix HY57V161610DTC‑8^[2]]
↑ [16‑bit, 66 MHz,^[20] Samsung KM416S4030^[36] 16‑bit, 66 MHz,^[20] Samsung KM416S4030^[36]]
↑ [16‑bit, 22 MHz, Hitachi HM62256^[37] 16‑bit, 22 MHz, Hitachi HM62256^[37]]
↑ [16‑bit, 10 MHz^[20] 16‑bit, 10 MHz^[20]]
↑ [16‑bit, 2 MHz^[38] 16‑bit, 2 MHz^[38]]
↑ [2× 64‑bit connectors, 1× 16‑bit connector 2× 64‑bit connectors, 1× 16‑bit connector]
↑ [34 MHz 34 MHz]
↑ [50 MHz^[39] 50 MHz^[39]]
↑ [66.666667 MHz^[40]^[41] 66.666667 MHz^[40]^[41]]
↑ [8/16‑bit, 28–50 MHz 8/16‑bit, 28–50 MHz]
↑ [1/2× 64‑bit, 133 MHz^[42]^[43] 1/2× 64‑bit, 133 MHz^[42]^[43]]
↑ ^45.0 ^45.1 ^45.2 [128/256‑bit 128/256‑bit]
↑ ^46.0 ^46.1 ^46.2 ^46.3 [32/64‑bit 32/64‑bit]
↑ [64/128‑bit 64/128‑bit]

References

Sega arcade boards
Originating in arcades
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 VIC Dual G80 Zaxxon VCO Object System 1 LaserDisc Appoooh Hang-On System 2 System 16 OutRun Gigas X Board Y Board System 24 System 18 System 32 Model 1 Model 2 H1 Board Model 3
Console-based hardware
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SG-1000 System E System C Mega-Tech System Mega Play Sega Titan Video NAOMI Hikaru NAOMI 2 Atomiswave System SP Chihiro Triforce
PC-based hardware
05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Lindbergh Europa-R RingEdge RingWide RingEdge 2 Nu Nu 1.1 Nu 2 ALLS

Sega Dreamcast
Topics	Technical specifications (Hardware comparison) \| History (Development \| Release \| Decline and legacy \| Internet) \| List of games \| Magazine articles \| Promotional material \| Merchandise
Hardware	Japan (Special) \| Western Europe \| Eastern Europe \| North America \| Asia \| South America \| Australasia \| Africa
Add-ons	Dreamcast Karaoke \| Dreameye
Controllers	Controller \| Arcade Stick \| Fishing Controller \| Gun (Dream Blaster) \| Race Controller \| Maracas Controller (Third-party) \| Twin Stick \| Keyboard \| Mouse \| Third-party
Controller Add-ons	Jump Pack (Third-party) \| Microphone \| VMU (4x Memory Card \| Third-party)
Development Hardware	Dev.Box \| Controller Box \| Controller Function Checker \| Sound Box \| GD-Writer \| C1/C2 Checker \| Dev.Cas \| GD-ROM Duplicator
Online Services/Add-ons	Dreamarena \| SegaNet \| WebTV for Dreamcast \| Modem \| Modular Cable \| Modular Extension Cable \| Broadband Adapter \| Dreamphone
Connector Cables	Onsei Setsuzoku Cable \| RF Adapter \| Scart Cable \| S Tanshi Cable \| Stereo AV Cable \| VGA Box Dreamcast MIDI Interface Cable \| Neo Geo Pocket/Dreamcast Setsuzoku Cable \| Taisen Cable
Misc. Hardware	Action Replay CDX \| Code Breaker \| Kiosk \| MP3 DC \| MP3 DC Audio Player \| Official Case \| Treamcast
Third-party accessories	Controllers \| Controller converters \| Miscellaneous
Unreleased Accessories	DVD Player \| Zip Drive \| Swatch Access for Dreamcast \| VMU MP3 Player
Arcade Variants	NAOMI \| Atomiswave \| Sega Aurora

[125.26nbsp.3BMHz.2C.7F.27.22.60UNIQ--ref-00000003-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-00000006-QINU.60.22.27.7F_compared_to_the_Dreamcast.27s_100.26nbsp.3BMHz-3] [125 MHz,^[1]^[2] compared to the Dreamcast's 100 MHz 125 MHz,^[1]^[2] compared to the Dreamcast's 100 MHz]

[2_instructions_per_cycle-7] [2 instructions per cycle 2 instructions per cycle]

[7_floating-point_operations_per_cycle-8] [7 floating-point operations per cycle 7 floating-point operations per cycle]

[Scaled_for_high-end_arcade_technology.2C.7F.27.22.60UNIQ--ref-00000029-QINU.60.22.27.7F_with_parallel_ISP_cores_and_increased_PE_processing_elements_within_processor..7F.27.22.60UNIQ--ref-0000002C-QINU.60.22.27.7F_NAOMI_has_average_fillrate_of_1_gigapixel.2Fsec.2C.7F.27.22.60UNIQ--ref-0000002D-QINU.60.22.27.7F_twice_that_of_the_Dreamcast.27s_average_500_megapixels.2Fsec_fillrate..7F.27.22.60UNIQ--ref-00000030-QINU.60.22.27.7F-19] [Scaled for high-end arcade technology,^[13] with parallel ISP cores and increased PE processing elements within processor.^[14] NAOMI has average fillrate of 1 gigapixel/sec,^[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[15] Scaled for high-end arcade technology,^[13] with parallel ISP cores and increased PE processing elements within processor.^[14] NAOMI has average fillrate of 1 gigapixel/sec,^[3] twice that of the Dreamcast's average 500 megapixels/sec fillrate.^[15]]

[14_cycles.2Fpolygon_per_ISP_FPU.2C_51_floating-point_operations_per_polygon.2C_102_floating-point_operations_per_14_cycles.7F.27.22.60UNIQ--ref-00000037-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000003A-QINU.60.22.27.7F-23] [14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles^[17]^[18] 14 cycles/polygon per ISP FPU, 51 floating-point operations per polygon, 102 floating-point operations per 14 cycles^[17]^[18]]

[Flat.2FGouraud_shading.2C_43_bytes_double-buffered-28] [Flat/Gouraud shading, 43 bytes double-buffered Flat/Gouraud shading, 43 bytes double-buffered]

[Gouraud_shading.2C_62_bytes_double-buffered-29] [Gouraud shading, 62 bytes double-buffered Gouraud shading, 62 bytes double-buffered]

[Textured.2C_Gouraud_shading.2C_bump_mapping.2C_72_bytes_double-buffered-30] [Textured, Gouraud shading, bump mapping, 72 bytes double-buffered Textured, Gouraud shading, bump mapping, 72 bytes double-buffered]

[Textured.2C_Gouraud_shading.2C_modifier_volumes.2C_75_bytes_double-buffered-31] [Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered Textured, Gouraud shading, modifier volumes, 75 bytes double-buffered]

[Sprite.2C_quad.2C_192_bytes_double-buffered-32] [Sprite, quad, 192 bytes double-buffered Sprite, quad, 192 bytes double-buffered]

[8.C3.978_texture.2C_16_colors-34] [8×8 texture, 16 colors 8×8 texture, 16 colors]

[8.C3.978.C3.974-bit-35] [8×8×4-bit 8×8×4-bit]

[1024.C3.971024.C3.9724-bit-36] [1024×1024×24-bit 1024×1024×24-bit]

[2048.C3.972048.C3.9716-bit-38] [2048×2048×16-bit 2048×2048×16-bit]

[32_pixels.2Fcycle_per_ISP.2C.7F.27.22.60UNIQ--ref-00000066-QINU.60.22.27.7F_1_pixel_per_PE_.28processor_element.29.2C.7F.27.22.60UNIQ--ref-00000069-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-0000006C-QINU.60.22.27.7F_64_PE_.2832_PE_per_ISP.29.2C_3.2_gigapixels.2Fsec_per_ISP.7F.27.22.60UNIQ--ref-0000006D-QINU.60.22.27.7F-44] [32 pixels/cycle per ISP,^[27] 1 pixel per PE (processor element),^[14]^[28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP^[29] 32 pixels/cycle per ISP,^[27] 1 pixel per PE (processor element),^[14]^[28] 64 PE (32 PE per ISP), 3.2 gigapixels/sec per ISP^[29]] (Wayback Machine: 2000-08-23 20:47)

[10_pixels_per_cycle.2C_6_PEs_.28processor_elements.29_per_pixel.2C_500_megapixels.2Fsec_per_ISP-45] [10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP 10 pixels per cycle, 6 PEs (processor elements) per pixel, 500 megapixels/sec per ISP]

[60_layers_depth.2C_2_pixels_per_cycle.2C_32_PEs_per_pixel.2C_100_megapixels.2Fsec_per_ISP-46] [60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP 60 layers depth, 2 pixels per cycle, 32 PEs per pixel, 100 megapixels/sec per ISP]

[Same_as_pixel_rendering_fillrate-47] [Same as pixel rendering fillrate Same as pixel rendering fillrate]

[14_cycles_per_3_vertices.2C_per_ISP_FPU-48] [14 cycles per 3 vertices, per ISP FPU 14 cycles per 3 vertices, per ISP FPU]

[14_cycles.2Fpolygon_per_ISP_FPU.2C_200.2C000.E2.80.93317.2C000_polygons_per_scene.2C_100.E2.80.93400_pixels_per_polygon-49] [14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon 14 cycles/polygon per ISP FPU, 200,000–317,000 polygons per scene, 100–400 pixels per polygon]

[Bump_mapping.2C_200.2C000.E2.80.93260.2C000_polygons_per_scene.2C_100.E2.80.93500_texels_per_polygon-50] [Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon Bump mapping, 200,000–260,000 polygons per scene, 100–500 texels per polygon]

[Bump_mapping.2C_100.2C000.E2.80.93219.2C000_polygons_per_scene.2C_100.E2.80.93600_texels_per_polygon-51] [Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon Bump mapping, 100,000–219,000 polygons per scene, 100–600 texels per polygon]

[138.2C888_polygons_per_scene.2C_100.E2.80.93700_texels_per_polygon-52] [138,888 polygons per scene, 100–700 texels per polygon 138,888 polygons per scene, 100–700 texels per polygon]

[137.2C664_polygons_per_scene.2C.7F.27.22.60UNIQ--ref-00000078-QINU.60.22.27.7F_100.E2.80.93700_texels_per_polygon-54] [137,664 polygons per scene,^[30] 100–700 texels per polygon 137,664 polygons per scene,^[30] 100–700 texels per polygon]

[122.2C958_.5B.5Bbyte.5D.5Ds-55] [122,958 bytes 122,958 bytes]

[26.2C178_bytes:_8_KB_instruction_cache.2C_16_KB_data_cache.2C_64_bytes_store_queue_cache.2C_1538_bytes_registers-56] [26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers 26,178 bytes: 8 KB instruction cache, 16 KB data cache, 64 bytes store queue cache, 1538 bytes registers]

[47.2C104_bytes:_8.25_KB_register_memory.2C_24.5_KB_ISP_cache.2C_13_KB_TSP_cache.2C_256_bytes_FIFO_buffer-57] [47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer 47,104 bytes: 8.25 KB register memory, 24.5 KB ISP cache, 13 KB TSP cache, 256 bytes FIFO buffer]

[32.2C780_bytes:_32_KB_sound_registers.2C_8_bytes_RTC_registers.2C_4_bytes_FIFO_buffer-58] [32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer 32,780 bytes: 32 KB sound registers, 8 bytes RTC registers, 4 bytes FIFO buffer]

[16.2C896_bytes:_512.26nbsp.3Bbytes_RAM.2C_16.26nbsp.3BKB_ROM.7F.27.22.60UNIQ--ref-00000083-QINU.60.22.27.7F-59] [16,896 bytes: 512 bytes RAM, 16 KB ROM^[7] 16,896 bytes: 512 bytes RAM, 16 KB ROM^[7]]

[128.E2.80.91bit.2C_200.26nbsp.3BMHz-62] [128‑bit, 200 MHz 128‑bit, 200 MHz]

[2304.E2.80.91bit.2C_100_MHz:_32-bit_TA_tile_buffer.2C.7F.27.22.60UNIQ--ref-00000092-QINU.60.22.27.7F_2x_32-bit_ISP_registers.2C_32-bit_TSP_registers.2C.7F.27.22.60UNIQ--ref-00000093-QINU.60.22.27.7F_2x_1024-bit_ISP_PE_Arrays.2C.7F.27.22.60UNIQ--ref-00000096-QINU.60.22.27.7F_64-bit_TSP_Texture_Cache.2C.7F.27.22.60UNIQ--ref-00000099-QINU.60.22.27.7F_32-bit_TSP_Tile_Accumulation_Buffer.2C_32-bit_Secondary_Accumulation_Buffer-65] [2304‑bit, 100 MHz: 32-bit TA tile buffer,^[33] 2x 32-bit ISP registers, 32-bit TSP registers,^[34] 2x 1024-bit ISP PE Arrays,^[14] 64-bit TSP Texture Cache,^[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer 2304‑bit, 100 MHz: 32-bit TA tile buffer,^[33] 2x 32-bit ISP registers, 32-bit TSP registers,^[34] 2x 1024-bit ISP PE Arrays,^[14] 64-bit TSP Texture Cache,^[27] 32-bit TSP Tile Accumulation Buffer, 32-bit Secondary Accumulation Buffer]

[32.E2.80.91bit.2C_67.26nbsp.3BMHz-66] [32‑bit, 67 MHz 32‑bit, 67 MHz]

[64.E2.80.91bit.2C_100.26nbsp.3BMHz.2C_Hitachi_HM5264165FTT.E2.80.91A60.7F.27.22.60UNIQ--ref-0000009E-QINU.60.22.27.7F-68] [64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60^[35] 64‑bit, 100 MHz, Hitachi HM5264165FTT‑A60^[35]]

[64.E2.80.91bit.2C_125.26nbsp.3BMHz.2C_.5B.5Bwikipedia:SK_Hynix.7CHynix.5D.5D_HY57V161610DTC.E2.80.918.7F.27.22.60UNIQ--ref-000000A2-QINU.60.22.27.7F-69] [64‑bit, 125 MHz, Hynix HY57V161610DTC‑8^[2] 64‑bit, 125 MHz, Hynix HY57V161610DTC‑8^[2]]

[16.E2.80.91bit.2C_66.26nbsp.3BMHz.2C.7F.27.22.60UNIQ--ref-000000A6-QINU.60.22.27.7F_.5B.5BSamsung.5D.5D_KM416S4030.7F.27.22.60UNIQ--ref-000000A9-QINU.60.22.27.7F-71] [16‑bit, 66 MHz,^[20] Samsung KM416S4030^[36] 16‑bit, 66 MHz,^[20] Samsung KM416S4030^[36]]

[16.E2.80.91bit.2C_22.26nbsp.3BMHz.2C_Hitachi_HM62256.7F.27.22.60UNIQ--ref-000000AD-QINU.60.22.27.7F-73] [16‑bit, 22 MHz, Hitachi HM62256^[37] 16‑bit, 22 MHz, Hitachi HM62256^[37]]

[16.E2.80.91bit.2C_10.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000B1-QINU.60.22.27.7F-74] [16‑bit, 10 MHz^[20] 16‑bit, 10 MHz^[20]]

[16.E2.80.91bit.2C_2.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000B5-QINU.60.22.27.7F-76] [16‑bit, 2 MHz^[38] 16‑bit, 2 MHz^[38]]

[2.C3.97.26nbsp.3B64.E2.80.91bit_connectors.2C_1.C3.97.26nbsp.3B16.E2.80.91bit_connector-77] [2× 64‑bit connectors, 1× 16‑bit connector 2× 64‑bit connectors, 1× 16‑bit connector]

[34.26nbsp.3BMHz-78] [34 MHz 34 MHz]

[50.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000BB-QINU.60.22.27.7F-80] [50 MHz^[39] 50 MHz^[39]]

[66.666667.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000BD-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000C0-QINU.60.22.27.7F-83] [66.666667 MHz^[40]^[41] 66.666667 MHz^[40]^[41]]

[8.2F16.E2.80.91bit.2C_28.E2.80.9350_MHz-84] [8/16‑bit, 28–50 MHz 8/16‑bit, 28–50 MHz]

[1.2F2.C3.97.26nbsp.3B64.E2.80.91bit.2C_133.26nbsp.3BMHz.7F.27.22.60UNIQ--ref-000000C5-QINU.60.22.27.7F.7F.27.22.60UNIQ--ref-000000C8-QINU.60.22.27.7F-87] [1/2× 64‑bit, 133 MHz^[42]^[43] 1/2× 64‑bit, 133 MHz^[42]^[43]]

[128.2F256.E2.80.91bit-88] 45.0 ^45.1 ^45.2 [128/256‑bit 128/256‑bit]

[32.2F64.E2.80.91bit-89] 46.0 ^46.1 ^46.2 ^46.3 [32/64‑bit 32/64‑bit]

[64.2F128.E2.80.91bit-90] [64/128‑bit 64/128‑bit]

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fmame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fnaomi.cpp_Sega_NAOMI_.28MAME.29.5D-1] 1.0 ^1.1 ^1.2 ^1.3 ^1.4 Sega NAOMI (MAME)

[:File:HY57V161610D_datasheet.pdf_p-2] 2.0 ^2.1 File:HY57V161610D datasheet.pdf

[Press_release:_1998-09-17:_SEGA_SELECTS_POWERVR_SERIES2_AS_3D_GRAPHICS_TECHNOLOGY_FOR_NEW_ARCADE_SYSTEM-4] 3.0 ^3.1 ^3.2 Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM

[:File:NAOMI_1998_Press_Release_JP.pdf_p-5] 4.0 ^4.1 File:NAOMI 1998 Press Release JP.pdf

[:File:SH-4_Software_Manual.pdf_p-6] File:SH-4 Software Manual.pdf

[.5Bhttp:.2F.2Fwww.drolez.com.2Fretro.2F_Obsolete_Microprocessors.5D-9] Obsolete Microprocessors

[:File:TMP90PH44_datasheet.pdf_p-10] 7.0 ^7.1 File:TMP90PH44 datasheet.pdf

[:File:PIC12C508A_datasheet.pdf_p-11] 8.0 ^8.1 File:PIC12C508A datasheet.pdf

[:File:PIC16C621A_datasheet.pdf_p-12] 9.0 ^9.1 File:PIC16C621A datasheet.pdf

[:File:EPF8452A_datasheet.pdf_p-13] File:EPF8452A datasheet.pdf

[:File:EPC1064_datasheet.pdf_p-14] File:EPC1064 datasheet.pdf

[.5Bhttps:.2F.2Fgithub.com.2Fmamedev.2Fhistoric-mame.2Fblob.2Fmaster.2Fsrc.2Fmame.2Fdrivers.2Fnaomi.c_Sega_NAOMI_.28Historic_MAME.29.5D-15] 12.0 ^12.1 Sega NAOMI (Historic MAME)

[:File:PowerVR.pdf_p2-16] File:PowerVR.pdf, page 2

[:File:PowerVR.pdf_p3-17] 14.0 ^14.1 ^14.2 ^14.3 File:PowerVR.pdf, page 3

[:File:Edge_UK_067.pdf_p11-18] File:Edge UK 067.pdf, page 11

[:File:DreamcastDevBoxSystemArchitecture.pdf_p110-20] File:DreamcastDevBoxSystemArchitecture.pdf, page 110

[:File:DreamcastDevBoxSystemArchitecture.pdf_p95-21] 17.0 ^17.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 95

[:File:DreamcastDevBoxSystemArchitecture.pdf_p203-22] File:DreamcastDevBoxSystemArchitecture.pdf, page 203

[:File:BU142_datasheet.pdf_p-24] File:BU142 datasheet.pdf

[:File:DreamcastDevBoxSystemArchitecture.pdf_p-25] 20.0 ^20.1 ^20.2 ^20.3 File:DreamcastDevBoxSystemArchitecture.pdf

[:File:DreamcastDevBoxSystemArchitecture.pdf_p102-26] File:DreamcastDevBoxSystemArchitecture.pdf, page 102

[:File:DreamcastDevBoxSystemArchitecture.pdf_p152-27] File:DreamcastDevBoxSystemArchitecture.pdf, page 152

[:File:DreamcastDevBoxSystemArchitecture.pdf_p199-33] File:DreamcastDevBoxSystemArchitecture.pdf, page 199

[:File:PowerVR2DCFeaturesUnderWindowsCE.pdf_p9-37] File:PowerVR2DCFeaturesUnderWindowsCE.pdf, page 9

[:File:DreamcastDevBoxSystemArchitecture.pdf_p144-39] File:DreamcastDevBoxSystemArchitecture.pdf, page 144

[.5Bhttp:.2F.2Ffarm6.staticflickr.com.2F5471.2F12172411045_18bfc5912f_c.jpg_Hideki_Sato_Sega_Interview_.28Edge.29.5D-40] 26.0 ^26.1 Hideki Sato Sega Interview (Edge)

[:File:DreamcastDevBoxSystemArchitecture.pdf_p96-41] 27.0 ^27.1 File:DreamcastDevBoxSystemArchitecture.pdf, page 96

[:File:Patent_US20030025695.pdf_p-42] File:Patent US20030025695.pdf

[.5Bhttp:.2F.2Fweb.archive.org.2Fweb.2F20000823204755.2Fcomputer.org.2Fmicro.2Farticles.2Fdreamcast_2.htm_Sega_Dreamcast:_Implementation_.28IEEE.29.5D-43] Sega Dreamcast: Implementation (IEEE) (Wayback Machine: 2000-08-23 20:47)

[.5Bhttp:.2F.2Fdknute.livejournal.com.2F27148.html_Homebrew_Test.5D-53] Homebrew Test

[.5Bhttp:.2F.2Fwww.mamedb.com.2Fgame.2Fasndynmt_Asian_Dynamite_.28MAME.29.5D-60] Asian Dynamite (MAME)

[:File:XCF01S_datasheet.pdf_p-61] File:XCF01S datasheet.pdf

[:File:DreamcastDevBoxSystemArchitecture.pdf_p165-63] File:DreamcastDevBoxSystemArchitecture.pdf, page 165

[.5Bhttp:.2F.2Fmc.pp.se.2Fdc.2Fpvr.html_PowerVR_.28Dreamcast_Hardware.29.5D-64] PowerVR (Dreamcast Hardware)

[:File:HM5264_datasheet.pdf_p-67] File:HM5264 datasheet.pdf

[:File:KM416S4030C_datasheet.pdf_p-70] File:KM416S4030C datasheet.pdf

[:File:HM62256B_datasheet.pdf_p-72] File:HM62256B datasheet.pdf

[:File:AT93C46_datasheet.pdf_p-75] File:AT93C46 datasheet.pdf

[:File:S29GL-N_datasheet.pdf_p-79] File:S29GL-N datasheet.pdf

[.5Bhttp:.2F.2Fmembers.iinet.net.au.2F.7Elantra9jp1.2Fgurudumps.2Fnaomi.2Findex.html_Sega_NAOMI_.28ROM_Dumping.29.5D-81] Sega NAOMI (ROM Dumping)

[:File:DA28F640J5_datasheet.pdf_p-82] File:DA28F640J5 datasheet.pdf

[.5Bhttp:.2F.2Fwiki.arcadeotaku.com.2Fw.2FSega_Naomi_DIMM_board_and_GD-ROM_Sega_NAOMI_DIMM_board_and_GD-ROM.5D-85] 42.0 ^42.1 Sega NAOMI DIMM board and GD-ROM

[:File:M366S3323CT0_datasheet.pdf_p-86] File:M366S3323CT0 datasheet.pdf

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@@ Line 25: / Line 25: @@
 ==Hardware==
-The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same [[Hitachi]] [[SuperH|SH-4]] CPU, [[wikipedia:PowerVR|PowerVR Series 2]] GPU ([http://segatech.com/technical/gpu/index.html PVR2DC]), and [[Yamaha]] [[Yamaha Super Intelligent Sound Processor|AICA]] based sound system. While the CPU of the NAOMI and Dreamcast operate at the same clock frequency, the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a faster PowerVR2 graphics processor, faster [[VRAM]] bandwidth,{{ref|125&nbsp;MHz,{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}{{fileref|HY57V161610D datasheet.pdf}} compared to the Dreamcast's 100&nbsp;MHz|group=n}} and [[wikipedia:FPGA|FPGA]] providing additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance, or for a multi-monitor setup.
+The NAOMI shares the same basic system architecture as the Dreamcast, with both systems using the same [[Hitachi]] [[SuperH|SH-4]] CPU and [[Yamaha]] [[Yamaha Super Intelligent Sound Processor|AICA]] based sound system, along with different revisions of the [[wikipedia:PowerVR|PowerVR Series 2]] GPU architecture. While the CPU of the NAOMI and Dreamcast operate at the same clock frequency, the NAOMI packs twice as much system and graphics memory, four times as much sound memory, a faster PowerVR2 graphics processor, faster [[VRAM]] bandwidth,{{ref|125&nbsp;MHz,{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}}{{fileref|HY57V161610D datasheet.pdf}} compared to the Dreamcast's 100&nbsp;MHz|group=n}} and [[wikipedia:FPGA|FPGA]] processors with additional processing. Multiple NAOMI boards can also be 'stacked' together to achieve better graphics performance, or for a multi-monitor setup.
 After ''[[The House of the Dead 2]]'', a newer revision of the PowerVR2 graphics chip was used in subsequent NAOMI systems.{{ref|[https://github.com/mamedev/mame/blob/master/src/mame/drivers/naomi.cpp Sega NAOMI (MAME)]}} According to VideoLogic's president and CEO, Hossein Yassaie, in September 1998: "''With Dreamcast, PowerVR set out to create a new standard in 3D graphics for console gaming; now with Sega’s Naomi, we will deliver unprecedented levels of 3D performance to arcade systems''".{{intref|Press release: 1998-09-17: SEGA SELECTS POWERVR SERIES2 AS 3D GRAPHICS TECHNOLOGY FOR NEW ARCADE SYSTEM}}

Difference between revisions of "Sega NAOMI"

From Sega Retro

Revision as of 04:54, 2 December 2016

Contents

History

Hardware

Technical Specifications

NAOMI Specifications

Main

Graphics

Sound

Memory

Bandwidth

NAOMI GD-ROM Specifications

Memory

Bandwidth

NAOMI Multiboard Specifications

Main

Graphics

Sound

Memory

Bandwidth

Gallery

First Edition

Main version

List of Games

NAOMI

Distributed by Capcom

Distributed by Namco

NAOMI GD-ROM

Distributed by Capcom

Distributed by Taito

NAOMI Multiboard

NAOMI Satellite Terminal

Promotional material

Notes

References